On 05/15/2013 07:55 AM, Jay Agarwal wrote:
Moving PCIe controller node to correct place so that it is sorted by
register address in .dtsi file
Reviewed-by: Stephen Warren swar...@nvidia.com
Hi Thierry,
If reviews are done, Can you please include this into your repository?
--
To
This series introduce CPU core power down state for CPU idle. When CPU go
into this state, it saves it's context and needs a proper configuration
in flow controller to power gate the CPU when CPU runs into WFI
instruction. And the CPU also needs to set the IRQ as CPU power down idle
wake up event
There is a difference between GICv1 and v2 when CPU in power management
mode (aka CPU power down on Tegra). For GICv1, IRQ/FIQ interrupt lines
going to CPU are same lines which are also used for wake-interrupt.
Therefore, we cannot disable the GIC CPU interface if we need to use same
interrupts
The flow controller would take care the power sequence when CPU idle in
powered-down mode. It powered gate the CPU when CPU runs into WFI
instruction. And wake up the CPU when event be triggered.
The sequence is below.
* setting wfi bitmap for the CPU as the halt event in the
On 05/30/2013 01:19 PM, Joseph Lo wrote:
This supports CPU core power down on each CPU when CPU idle. When CPU go
into this state, it saves it's context and needs a proper configuration
in flow controller to power gate the CPU when CPU runs into WFI
instruction. And the CPU also needs to set
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On 05/29/2013 04:10 AM, Jay Agarwal wrote:
So, if I apply this series, I do see the PCIe bridge and Ethernet
device get enumerated, but I don't see the USB3 controller get
enumerated. I believe that is a PCIe device behind the same bridge
on the
same Tegra PCIe port.
Shouldn't this
On 05/30/2013 11:37 AM, Jay Agarwal wrote:
...
I have taken care of all your comments, but Ethernet device is not working
for me neither on cardhu nor harmony.
Could be related to my process or board, Currently debugging this.
Are you talking about a PCIe-based Ethernet device on Harmony, or
On Mon, May 27, 2013 at 03:14:30PM +0300, Andy Shevchenko wrote:
Here is a set of small independent patches that clean up or fix minor things
across DMA slave drivers.
The series looks fine. I am going to wait a day more and apply, pls speak up if
you disagree and ack if you agree
--
~Vinod
On Thu, May 30, 2013 at 8:47 PM, Vinod Koul vinod.k...@intel.com wrote:
On Mon, May 27, 2013 at 03:14:30PM +0300, Andy Shevchenko wrote:
Here is a set of small independent patches that clean up or fix minor things
across DMA slave drivers.
The series looks fine. I am going to wait a day more
On Mon, May 13, 2013 at 09:34:05AM +0530, Laxman Dewangan wrote:
On Saturday 11 May 2013 10:00 PM, Dmitry Osipenko wrote:
Fixed err msg params order on irq request fail.
Signed-off-by: Dmitry Osipenko dig...@gmail.com
Acked-by: Stephen Warren swar...@nvidia.com
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Looks good to me for
On Mon, May 13, 2013 at 10:20:36AM -0600, Stephen Warren wrote:
On 05/11/2013 10:30 AM, Dmitry Osipenko wrote:
Lock scenario: Channel 1 was allocated and prepared as slave_sg, used and
freed.
Now preparation of cyclic dma on channel 1 will fail with err DMA
configuration
conflict
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