Hi Wuqiang, On Thu, 26 Oct 2023 19:05:51 +0800 "wuqiang.matt" <wuqiang.m...@bytedance.com> wrote:
> On 2023/10/26 16:46, Arnd Bergmann wrote: > > On Thu, Oct 26, 2023, at 09:39, wuqiang.matt wrote: > >> arch_cmpxchg[64]_local() are not defined for openrisc. So implement > >> them with generci_cmpxchg[64]_local, advised by Masami Hiramatsu. > >> > >> Closes: > >> https://lore.kernel.org/linux-trace-kernel/169824660459.24340.14614817132696360531.stgit@devnote2 > >> Closes: > >> https://lore.kernel.org/oe-kbuild-all/202310241310.ir5uukog-...@intel.com > >> > >> Signed-off-by: wuqiang.matt <wuqiang.m...@bytedance.com> > > > > I think on architectures that have actual atomics, you > > generally want to define this to be the same as arch_cmpxchg() > > rather than the generic version. > > > > It depends on the relative cost of doing one atomic compared > > to an irq-disable/enable pair, but everyone else went with > > the former if they could. The exceptions are armv4/armv5, > > sparc32 and parisc, which don't have a generic cmpxchg() > > or similar operation. > > Sure, better native than the generic. I'll try to collect more > insights before next move. So I will temporally remove the last change (use arch_cmpxchg_local in objpool) until these series are rewritten with arch native code, so that the next release will not break the kernel build. But this must be fixed because arch_cmpxchg_local() is required for each arch anyway. > > > You could do the thing that sparc64 and xtensa do, which > > use the native cmpxchg for supported word sizes but the > > generic version for 1- and 2-byte swaps, but that has its > > own set of problems if you end up doing operations on both > > the entire word and a sub-unit of the same thing. > > Thank you for pointing out this. I'll do some research on these > implementations. arc also has the LL-SC instruction but depends on the core feature, so I think we can use it. Thank you, > > > Arnd > > Regards, > wuqiang > -- Masami Hiramatsu (Google) <mhira...@kernel.org>
