Hi Greg,
This patch fixes a hang issue if phy clock is not there and we want
to configure phy through portsc.pts.
Peter Chen (1):
usb: chipidea: coordinate usb phy initialization for different phy
type
drivers/usb/chipidea/core.c | 37 ++---
1 files
On Tue, 2014-04-22 at 16:30 +0100, Srinivas Kandagatla wrote:
On 22/04/14 10:20, Ivan T. Ivanov wrote:
@@ -79,8 +78,7 @@ static int msm_hsusb_init_vddcx(struct msm_otg *motg, int
init)
ret = regulator_set_voltage(motg-vddcx, 0,
USB_PHY_VDD_DIG_VOL_MAX);
On 04/22/2014 05:03 PM, Aaro Koskinen wrote:
Hi,
On Tue, Apr 22, 2014 at 08:21:35AM +0200, Robert Baldyga wrote:
On 04/19/2014 12:52 PM, Aaro Koskinen wrote:
On Mon, Apr 14, 2014 at 01:46:16PM +0200, Robert Baldyga wrote:
dev_info(pdev-dev,
- OMAP USB OTG controller rev %d.%d
Hi Alan,
On Tue, Apr 22, 2014 at 11:28 PM, Alan Stern st...@rowland.harvard.edu wrote:
Thanks for reviewing this. Please find my comments inline below.
On Thu, 10 Apr 2014, Vivek Gautam wrote:
Add support to consume phy provided by Generic phy framework.
Keeping the support for older
Hi,
On Tue, Apr 22, 2014 at 11:29 PM, Alan Stern st...@rowland.harvard.edu wrote:
On Tue, 22 Apr 2014, Vivek Gautam wrote:
On Thu, Apr 10, 2014 at 6:54 PM, Vivek Gautam gautam.vi...@samsung.com
wrote:
Add support to consume phy provided by Generic phy framework.
Keeping the support for
On Wednesday 26 March 2014 13:38:29, Oliver Neukum wrote:
On Wed, 2014-03-26 at 13:18 +0100, Alexander Stein wrote:
On Wednesday 26 March 2014 12:38:24, Oliver Neukum wrote:
On Tue, 2014-03-25 at 10:34 +0100, Alexander Stein wrote:
As the module does not use the standard USB mechanism,
On Tue, Apr 22, 2014 at 08:45:23AM +0800, Li Jun wrote:
From: Li Jun b47...@freescale.com
This patchset adds USB OTG HNP and SRP support on chipidea usb driver,
existing OTG port role swtich function by ID pin status kept unchanged,
based on that, if select CONFIG_USB_OTG_FSM, OTG HNP and
From: Denis Carikli de...@eukrea.com
This adds the i.MX25 and the i.MX35 support in the
ChipIdea usbmisc driver.
The i.MX25 and i.MX35 usb controllers are similar enough to be
able to use the same code.
Signed-off-by: Peter Chen peter.c...@freescale.com
Signed-off-by: Denis Carikli
After the PHY has powered and initialized, it needs some delay
for controller to reflect PHY's status. Some status and values
for id, vbus, dp/dm are only stable after this delay. The current
code tries to clear id/vbus status without enough delay, it
causes the status are not cleared properly.
From: Li Jun b47...@freescale.com
This patch exports symbol of otg_statemachine for kernel module
can use it.
Acked-by: Felipe Balbi ba...@ti.com
Signed-off-by: Peter Chen peter.c...@freescale.com
Signed-off-by: Li Jun b47...@freescale.com
---
drivers/usb/phy/phy-fsm-usb.c |1 +
1 files
Hi Greg,
We have finished USB OTG FSM (HNP SRP) support for chipidea
in this patchset, thanks for Jun's great work, others are some
small changes, including add some new SoC support, etc, thanks.
Best regards,
Peter
Alexander Shiyan (1):
usb: chipidea: core: Add missing module owner field
From: Li Jun b47...@freescale.com
Add b_hnp_enable request handling and enable gadget-is_otg
Signed-off-by: Peter Chen peter.c...@freescale.com
Acked-by: Peter Chen peter.c...@freescale.com
Signed-off-by: Li Jun b47...@freescale.com
---
drivers/usb/chipidea/udc.c | 11 ++-
1 files
From: Li Jun b47...@freescale.com
This patch adds a debug file for OTG vairables show.
Signed-off-by: Peter Chen peter.c...@freescale.com
Signed-off-by: Li Jun b47...@freescale.com
---
drivers/usb/chipidea/debug.c | 84 ++
1 files changed, 84
From: Li Jun b47...@freescale.com
This patch adds sysfs interface description for chipidea USB OTG HNP and SRP.
Signed-off-by: Peter Chen peter.c...@freescale.com
Signed-off-by: Li Jun b47...@freescale.com
---
.../ABI/testing/sysfs-platform-chipidea-usb-otg| 56
1
From: Li Jun b47...@freescale.com
Add OTG HNP and SRP operation functions implementation:
- charge vbus
- drive vbus
- connection signaling
- drive sof
- start data pulse
- add fsm timer
- delete fsm timer
- start host
- start gadget
Signed-off-by: Peter Chen peter.c...@freescale.com
From: Li Jun b47...@freescale.com
This patch adds OTG fsm timers initialization, which use controller's 1ms
interrupt as timeout counter, also adds some local timers which are not
in otg_fsm_timer list.
Signed-off-by: Peter Chen peter.c...@freescale.com
Signed-off-by: Li Jun b47...@freescale.com
From: Li Jun b47...@freescale.com
This patch adds OTG fsm related initialization when do otg init,
add a seperate file for OTG fsm related utilities.
Signed-off-by: Peter Chen peter.c...@freescale.com
Signed-off-by: Li Jun b47...@freescale.com
---
drivers/usb/chipidea/Makefile |1 +
From: Li Jun b47...@freescale.com
Init otg_port number of otg capable host to be 1 at host start.
Signed-off-by: Peter Chen peter.c...@freescale.com
Signed-off-by: Li Jun b47...@freescale.com
---
drivers/usb/chipidea/host.c | 11 +--
1 files changed, 9 insertions(+), 2 deletions(-)
From: Li Jun b47...@freescale.com
This patch adds sys input to control and show OTG fsm inputs by application,
user can do host and preipheral role switch by change these inputs.
Signed-off-by: Peter Chen peter.c...@freescale.com
Signed-off-by: Li Jun b47...@freescale.com
---
For internal PHY (like UTMI), the phy clock may from internal pll,
it is on/off on the fly, the access PORTSC.PTS will hang without
phy clock. So, the usb_phy_init which will open phy clock needs to
be called before hw_phymode_configure.
See:
Hello,
-Original Message-
From: Vivek Gautam [mailto:gautamvivek1...@gmail.com] On Behalf Of
Vivek Gautam
Sent: Monday, April 21, 2014 9:17 PM
To: linux-usb@vger.kernel.org; linux-samsung-...@vger.kernel.org
Cc: linux-ker...@vger.kernel.org; linux-o...@vger.kernel.org; linux-
On Tue, Apr 22, 2014 at 12:43:14PM +0300, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
This series intend to fix driver, which was broken for a while.
It is used to create peripheral role device, which in coordination
with phy-usb-msm driver could provide USB2.0 gadget
Fix driver new_id sysfs-attribute removal deadlock by making sure to
not hold any locks that the attribute operations grab when removing the
attribute.
Specifically, usb_serial_deregister holds the table mutex when
deregistering the driver, which includes removing the new_id attribute.
This can
Hi Anton,
On Wed, Apr 23, 2014 at 2:56 PM, Anton Tikhomirov
av.tikhomi...@samsung.com wrote:
Hello,
-Original Message-
From: Vivek Gautam [mailto:gautamvivek1...@gmail.com] On Behalf Of
Vivek Gautam
Sent: Monday, April 21, 2014 9:17 PM
To: linux-usb@vger.kernel.org;
Hi,
Hi Anton,
On Wed, Apr 23, 2014 at 2:56 PM, Anton Tikhomirov
av.tikhomi...@samsung.com wrote:
Hello,
-Original Message-
From: Vivek Gautam [mailto:gautamvivek1...@gmail.com] On Behalf Of
Vivek Gautam
Sent: Monday, April 21, 2014 9:17 PM
To:
Hi,
On Wed, Apr 23, 2014 at 4:27 PM, Anton Tikhomirov
av.tikhomi...@samsung.com wrote:
Hi,
Hi Anton,
On Wed, Apr 23, 2014 at 2:56 PM, Anton Tikhomirov
av.tikhomi...@samsung.com wrote:
Hello,
-Original Message-
From: Vivek Gautam [mailto:gautamvivek1...@gmail.com] On Behalf
W dniu 20.04.2014 21:33, Robert Jarzmik pisze:
Robert Jarzmik robert.jarz...@free.fr writes:
Hi,
I've tried the 3.15-rc1 recently. Upon USB gether gadget connexion, the kernel
panics. With 3.14, no issue is seen.
And if I revert commit in [2], everything works fine.
That should speed up the
From: Ivan T. Ivanov iiva...@mm-sol.com
Allows controller to be specified via device tree.
Pass PHY phandle specified in DT to core driver.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
drivers/usb/chipidea/ci_hdrc_msm.c | 23 ++-
1 file changed, 22 insertions(+), 1
On Wednesday, April 23, 2014 8:06 PM, Vivek Gautam wrote:
On Wednesday, April 23, 2014 7:58 PM, Anton Tikhomirov wrote:
On Wednesday, April 23, 2014 6:52 PM, Vivek Gautam wrote:
On Wednesday, April 23, 2014 6:27 PM, Anton Tikhomirov wrote:
On Monday, April 21, 2014 9:17 PM, Vivek Gautam
From: Ivan T. Ivanov iiva...@mm-sol.com
Since commit 62bb84e (usb: gadget: ci13xxx: convert to platform device)
start address of the capability registers is not passed correctly to
udc_probe(). Fix this.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
drivers/usb/chipidea/ci_hdrc_msm.c | 1
On Monday, April 21, 2014 9:17 PM, Vivek Gautam wrote:
Facilitate getting required 3.3V and 1.0V VDD supply for
OHCI controller on Exynos.
With patches for regulators' nodes merged in 3.15:
c8c253f ARM: dts: Add regulator entries to smdk5420
275dcd2 ARM: dts: add max77686 pmic node for
On Monday, April 21, 2014 9:17 PM, Vivek Gautam wrote:
Facilitate getting required 3.3V and 1.0V VDD supply for
EHCI controller on Exynos.
With patches for regulators' nodes merged in 3.15:
c8c253f ARM: dts: Add regulator entries to smdk5420
275dcd2 ARM: dts: add max77686 pmic node for
From: Ivan T. Ivanov iiva...@mm-sol.com
Document device tree binding information as required by
the Qualcomm USB controller.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
Documentation/devicetree/bindings/usb/ci-hdrc-qcom.txt | 17 +
1 file changed, 17 insertions(+)
Hello.
On 23-04-2014 17:35, Ivan T. Ivanov wrote:
--- a/include/linux/usb/msm_hsusb_hw.h
+++ b/include/linux/usb/msm_hsusb_hw.h
@@ -31,8 +31,9 @@
#define USB_USBINTR (MSM_USB_BASE + 0x0148)
#define PORTSC_PHCD(1 23) /* phy suspend mode */
-#define PORTSC_PTS_MASK
On Wed, 2014-04-23 at 17:45 +0400, Sergei Shtylyov wrote:
Hello.
On 23-04-2014 17:35, Ivan T. Ivanov wrote:
--- a/include/linux/usb/msm_hsusb_hw.h
+++ b/include/linux/usb/msm_hsusb_hw.h
@@ -31,8 +31,9 @@
#define USB_USBINTR (MSM_USB_BASE + 0x0148)
#define
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And
On 23-04-2014 17:53, Ivan T. Ivanov wrote:
--- a/include/linux/usb/msm_hsusb_hw.h
+++ b/include/linux/usb/msm_hsusb_hw.h
@@ -31,8 +31,9 @@
#define USB_USBINTR (MSM_USB_BASE + 0x0148)
#define PORTSC_PHCD(1 23) /* phy suspend mode */
-#define PORTSC_PTS_MASK
On Wed, 2014-04-23 at 18:09 +0400, Sergei Shtylyov wrote:
On 23-04-2014 17:53, Ivan T. Ivanov wrote:
--- a/include/linux/usb/msm_hsusb_hw.h
+++ b/include/linux/usb/msm_hsusb_hw.h
@@ -31,8 +31,9 @@
#define USB_USBINTR (MSM_USB_BASE + 0x0148)
#define PORTSC_PHCD
cc'ing Li Zhong who's working on a simliar issue in the following
thread and quoting whole body.
http://thread.gmane.org/gmane.linux.kernel/1680706
Li, this is another variation of the same problem. Maybe this can be
covered by your work too?
Thanks.
On Wed, Apr 23, 2014 at 11:32:19AM
Removing this older USB 3.0 DRD controller PHY driver, since
a new driver based on generic phy framework is now available.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
This is reworked version for the patch :
[PATCH V4 5/5] usb-phy:
After removing the phy-samsung-usb3 driver, this config
should be removed.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
arch/arm/configs/exynos_defconfig |1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/configs/exynos_defconfig
b/arch/arm/configs/exynos_defconfig
index
Add required fixed-regulator for VBUS supply for USB 3.0
controller phy.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
This is first version of the patch for VBUS support for USB3DRD phy.
v5 is just and indicative of the patch-series.
arch/arm/boot/dts/exynos5420-smdk5420.dts | 46
Hello.
On 23-04-2014 18:14, Ivan T. Ivanov wrote:
--- a/include/linux/usb/msm_hsusb_hw.h
+++ b/include/linux/usb/msm_hsusb_hw.h
@@ -31,8 +31,9 @@
#define USB_USBINTR (MSM_USB_BASE + 0x0148)
#define PORTSC_PHCD(1 23) /* phy suspend mode */
-#define
Removing the dt node for older usb3 phy driver from Exynos5250
device tree and updating the dt node for DWC3 controller to
use new phy driver based on generic phy framework.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
Add device tree nodes for DWC3 controller present on
Exynos 5420 SoC, to enable support for USB 3.0.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/boot/dts/exynos5420.dtsi | 34 ++
1 file changed,
Add device tree nodes for USB 3.0 PHY present alongwith
USB 3.0 controller Exynos 5420 SoC. This phy driver is
based on generic phy framework.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/boot/dts/exynos5420.dtsi | 20
Add device tree node for new usbdrd-phy driver, which
is based on generic phy framework.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/boot/dts/exynos5250.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git
Based on 'for-next' branch of Kgene's linux-samsung tree.
Tested with phy-driver[1] patches and peach-pit dts[2].
This is the DT split part of the patch-series[3].
Patches: usb-phy: samsung-usb3: Remove older phy-samsung-usb3 driver
ARM: exynos_defconfig: Remove SAMSUNG_USB3PHY config
On Wed, Apr 23, 2014 at 11:48:29AM +0300, Ivan T. Ivanov wrote:
On Tue, 2014-04-22 at 10:24 -0500, Felipe Balbi wrote:
On Tue, Apr 22, 2014 at 06:16:35PM +0300, Ivan T. Ivanov wrote:
Hi,
On Tue, 2014-04-22 at 09:57 -0500, Felipe Balbi wrote:
On Tue, Apr 22, 2014 at 12:20:20PM
On Wed, Apr 23, 2014 at 08:16:49AM +0800, Gavin Guo wrote:
Hi Sarah,
On Wed, Apr 23, 2014 at 7:57 AM, Sarah Sharp
sarah.a.sh...@linux.intel.com wrote:
[Adding Mathias, who is the xHCI driver maintainer as of 3.15.]
On Wed, Apr 23, 2014 at 07:23:43AM +0800, Gavin Guo wrote:
Hi
On Wed, Apr 23, 2014 at 02:13:46PM +0200, Andrzej Pietrasiewicz wrote:
W dniu 20.04.2014 21:33, Robert Jarzmik pisze:
Robert Jarzmik robert.jarz...@free.fr writes:
Hi,
I've tried the 3.15-rc1 recently. Upon USB gether gadget connexion, the
kernel
panics. With 3.14, no issue is seen.
Hi,
On Wed, Apr 23, 2014 at 09:44:57AM +0200, Gregory CLEMENT wrote:
On Fri, Apr 18, 2014 at 12:22:37PM +0200, Gregory CLEMENT wrote:
For the armada 38x SoCs which come with an xhci controller, specific
initialization must be done during probe, especially in relation with
the MBus windows
Add required VDD 3.3V and VDD 1.0V regulator supplies to usb nodes.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
arch/arm/boot/dts/exynos5420-smdk5420.dts | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts
Add required VDD 3.3V and VDD 1.0V regulator supplies to usb nodes.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
arch/arm/boot/dts/exynos5250-smdk5250.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
On 04/22/2014 04:19 PM, Ezequiel Garcia wrote:
The DMA controller is needed for the USB controller to be correctly
registered. Therefore, if the DMA node is located at the end an unecessary
probe deferral is produced systematically.
This is easily fixed by moving the node at the beggining of
Based on for-next branch of Kgene's linux-samsung tree, with
following patch series:
[PATCH 0/9] Enable USB 3.0 support on Exynos5 systems
https://lkml.org/lkml/2014/4/23/389
These are device tree patches corresponding to the usb driver patch-series:
[PATCH 1/3] usb: ohci-exynos: Make provision
Add required VDD 3.3V and VDD 1.0V regulator supplies to usb nodes.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
arch/arm/boot/dts/exynos5250-snow.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts
The following commit introduced the debugfs :
40f099e32c2a06bad7d75683421e30fcc74924cd
Author: Markus Pargmann m...@pengutronix.de
Date: Fri Jan 17 10:22:35 2014 +0100
usb: musb: dsps, debugfs files
Unfortunately, a forgotten call to a cleanup function prevents the
probing of musb in case
On Wed, Apr 23, 2014 at 05:39:43PM +0200, Olivier Gayot wrote:
The following commit introduced the debugfs :
40f099e32c2a06bad7d75683421e30fcc74924cd
Author: Markus Pargmann m...@pengutronix.de
Date: Fri Jan 17 10:22:35 2014 +0100
usb: musb: dsps, debugfs files
Unfortunately, a
On Wed, Apr 23, 2014 at 01:12:43PM +0900, Chanwoo Choi wrote:
This patch uses devm_extcon_dev_{allocate, register} function for
automatically
resource management of extcon device instead of legacy method and simplifies
the behavior of register/unregister for extcon device.
Signed-off-by:
On Apr 23, Sebastian Andrzej Siewior wrote:
On 04/22/2014 04:19 PM, Ezequiel Garcia wrote:
The DMA controller is needed for the USB controller to be correctly
registered. Therefore, if the DMA node is located at the end an unecessary
probe deferral is produced systematically.
This is
Hi Peter,
On Thu, Mar 27, 2014 at 2:23 AM, Peter Chen peter.c...@freescale.com wrote:
On Mon, Mar 24, 2014 at 11:55:17PM -0300, Fabio Estevam wrote:
From: Fabio Estevam fabio.este...@freescale.com
The field PLLDIVVALUE of register PHY_CTRL_1 selects the reference clock
source
for the PHY:
If no valid CHID value has previously been set on an HWA, writing a
value of all zeros will cause a kernel panic in uwb_radio_stop because
wusbhc-uwb_rc has not been set. This patch skips the call to
uwb_radio_stop if wusbhc-uwb_rc has not been initialized.
Signed-off-by: Thomas Pugliese
Nesting a spin_lock_irq/unlock_irq inside a lock that has already
disabled interrupts will enable interrupts before we are ready when
spin_unlock_irq is called. This patch converts the inner lock to use
spin_lock and spin_unlock instead.
Signed-off-by: Thomas Pugliese thomas.pugli...@gmail.com
Hi,
-Original Message-
From: linux-usb-ow...@vger.kernel.org [mailto:linux-usb-
ow...@vger.kernel.org] On Behalf Of Vivek Gautam
Sent: Monday, April 21, 2014 9:17 PM
Facilitate getting required 3.3V and 1.0V VDD supply for
OHCI controller on Exynos.
With patches for regulators'
On Thursday, April 24, 2014 9:18 AM, Anton Tikhomirov wrote:
On Monday, April 21, 2014 9:17 PM, Vivek Gautam wrote:
Facilitate getting required 3.3V and 1.0V VDD supply for
OHCI controller on Exynos.
With patches for regulators' nodes merged in 3.15:
c8c253f ARM: dts: Add regulator
Hi,
Hi,
-Original Message-
From: linux-usb-ow...@vger.kernel.org [mailto:linux-usb-
ow...@vger.kernel.org] On Behalf Of Vivek Gautam
Sent: Monday, April 21, 2014 9:17 PM
Facilitate getting required 3.3V and 1.0V VDD supply for
OHCI controller on Exynos.
With patches
For internal PHY (like UTMI), the phy clock may from internal pll,
it is on/off on the fly, the access PORTSC.PTS will hang without
phy clock. So, the usb_phy_init which will open phy clock needs to
be called before hw_phymode_configure.
See:
Hi Greg,
This patch fixes a hang issue if phy clock is not there and we want
to configure phy through portsc.pts.
P.S: Seems the patch is lost, so I re-send it.
Peter Chen (1):
usb: chipidea: coordinate usb phy initialization for different phy
type
drivers/usb/chipidea/core.c | 37
On Thursday, April 24, 2014 9:33 AM, Jingoo Han wrote:
On Thursday, April 24, 2014 9:18 AM, Anton Tikhomirov wrote:
On Monday, April 21, 2014 9:17 PM, Vivek Gautam wrote:
Facilitate getting required 3.3V and 1.0V VDD supply for
OHCI controller on Exynos.
With patches for
Hi Peter,
On Thu, Mar 27, 2014 at 2:23 AM, Peter Chen peter.c...@freescale.com
wrote:
On Mon, Mar 24, 2014 at 11:55:17PM -0300, Fabio Estevam wrote:
From: Fabio Estevam fabio.este...@freescale.com
The field PLLDIVVALUE of register PHY_CTRL_1 selects the reference
clock source
On Wed, Apr 23, 2014 at 9:15 PM, Peter Chen peter.c...@freescale.com wrote:
For internal PHY (like UTMI), the phy clock may from internal pll,
it is on/off on the fly, the access PORTSC.PTS will hang without
phy clock. So, the usb_phy_init which will open phy clock needs to
be called before
On Wed, Apr 23, 2014 at 10:30 PM, Peter Chen peter.c...@freescale.com wrote:
Oh, sorry. I forget to send it to Greg yesterday. If you can wait,
I will send it next time (within two weeks) with other patches,
if can't, I can send it today.
Ok, no need to hush. Just wanted to make sure that the
On Wed, Apr 23, 2014 at 03:28:01PM +0300, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
This series intend to fix driver, which was broken for a while.
It is used to create peripheral role device, which in coordination
with phy-usb-msm driver could provide USB2.0 gadget
On Wed, Apr 23, 2014 at 10:30 PM, Peter Chen peter.c...@freescale.com
wrote:
Oh, sorry. I forget to send it to Greg yesterday. If you can wait, I
will send it next time (within two weeks) with other patches, if
can't, I can send it today.
Ok, no need to hush. Just wanted to make
On Wed, Apr 23, 2014 at 9:15 PM, Peter Chen peter.c...@freescale.com
wrote:
For internal PHY (like UTMI), the phy clock may from internal pll, it
is on/off on the fly, the access PORTSC.PTS will hang without phy
clock. So, the usb_phy_init which will open phy clock needs to be
called
On Wed, Apr 23, 2014 at 10:58 PM, Peter Chen peter.c...@freescale.com wrote:
This patch can cover both ULPI DT support version in future and current
version
(can fix sasche's problem), in order to add something again in future, I
choose
to use a new patch.
Will be there a ULPI DT driver
On Thursday, April 24, 2014 10:14 AM, Fabio Estevam wrote:
On Wed, Apr 23, 2014 at 10:58 PM, Peter Chen peter.c...@freescale.com wrote:
This patch can cover both ULPI DT support version in future and current version
(can fix sasche's problem), in order to add something again in future, I
This patch can cover both ULPI DT support version in future and
current version (can fix sasche's problem), in order to add something
again in future, I choose to use a new patch.
Will be there a ULPI DT driver version? Isn't it what generic phy nop
driver already does?
Fabio,
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