I’m investigating the (lack of) performance (around 150MB/s) of the USB3380
gadget in mass storage mode.
Whilst tracing on a Linux 4.1 host I noticed that the Linux max storage driver
is requesting 240 blocks, 16 blocks, 240 blocks, 16 blocks, etc. when doing a
dd directly on the device:
On Mon, 5 Oct 2015, Paul Jones wrote:
> I�m investigating the (lack of) performance (around 150MB/s) of the USB3380
> gadget in mass storage mode.
> Whilst tracing on a Linux 4.1 host I noticed that the Linux max storage
> driver is requesting 240 blocks, 16 blocks, 240 blocks, 16 blocks, etc.
On Mon, 5 Oct 2015, Paul Jones wrote:
> > g_mass_storage, by default, uses 2 struct usb_request, try increasing that
> > to 4
> > (can be done from make menuconfig itself) and see if anything changes.
> If you are talking about the �number of storage pipeline buffers� I already
> have them at
From: Ben Shelton
The USB gadget support currently depends on power management
(CONFIG_PM) being enabled, but does not actually need it enabled.
Remove this dependency.
Tested on Bay Trail hardware with dwc3 USB.
Signed-off-by: Nathan Sullivan
---
On 05 Oct 2015, at 20:29, Alan Stern wrote:
> On Mon, 5 Oct 2015, Paul Jones wrote:
>
>> I�m investigating the (lack of) performance (around 150MB/s) of the USB3380
>> gadget in mass storage mode.
>> Whilst tracing on a Linux 4.1 host I noticed that the Linux max
On Mon, Oct 05, 2015 at 07:30:05PM +0200, Paul Jones wrote:
> I’m investigating the (lack of) performance (around 150MB/s) of the USB3380
> gadget in mass storage mode. Whilst tracing on a Linux 4.1 host I noticed
> that the Linux max storage driver is requesting 240 blocks, 16 blocks, 240
>
On Mon, 5 Oct 2015, Eugen Rogoza wrote:
> Hello,
>
> in xHCI mode I'm experiencing random disconnects and reconnects of my ASMedia
> ASM1051-based external HDD enclosure.
>
> The only combination where the disconnects are happening is Intel USB Host
> Controller + Linux kernel + XHCI mode
On 05 Oct 2015, at 20:08, Felipe Balbi wrote:
> On Mon, Oct 05, 2015 at 07:30:05PM +0200, Paul Jones wrote:
>> I’m investigating the (lack of) performance (around 150MB/s) of the USB3380
>> gadget in mass storage mode. Whilst tracing on a Linux 4.1 host I noticed
>> that the
Nathan Sullivan writes:
> From: Ben Shelton
>
> The USB gadget support currently depends on power management
> (CONFIG_PM) being enabled, but does not actually need it enabled.
> Remove this dependency.
>
> Tested on Bay Trail hardware with dwc3 USB.
On Monday, October 05, 2015 04:45:28 PM Tomeu Vizoso wrote:
> Hi,
>
> this is v9 of an attempt to make it easier for devices to remain in
> runtime PM when the system goes to sleep, mainly to reduce the time
> spent resuming devices.
>
> For this, we interpret the absence of all PM callback
Ramneek Mehresh writes:
> Add support for otg for all freescale socs having internal
> usb phy.
>
> Ramneek Mehresh (7):
> usb:fsl:otg: Make fsl otg driver as tristate
> usb:fsl:otg: Add controller version based ULPI and UTMI phy
> usb:fsl:otg: Add support to
This adds the PCI product ID for the Synopsys USB 3.1 IP core
(DWC_usb31) on a HAPS-based PCI development platform.
Cc: # v3.18+
Signed-off-by: John Youn
---
drivers/usb/dwc3/dwc3-pci.c | 5 +
1 file changed, 5 insertions(+)
diff --git
Add platform data and set usb3_lpm_capable and has_lpm_erratum.
Cc: # v3.18+
Signed-off-by: John Youn
---
drivers/usb/dwc3/dwc3-pci.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/usb/dwc3/dwc3-pci.c
This patch contains several updates to dwc3 to support Synopsys
platforms.
Patch 1: Initial support for 3.1 IP (applies to all platforms)
Patch 2-4: PCI id and platform data for Synopsys platforms
Patch 5-6: Add a quirk to program a global register
Patch 6: Formatting
Tested on Synopsys HAPS PCI
Bin Liu writes:
> Hi Felipe,
>
> On 09/24/2015 03:37 AM, Hans de Goede wrote:
>> Hi,
>>
>> On 23-09-15 22:59, Bin Liu wrote:
>>> Hi,
>>>
>>> On 09/23/2015 02:53 PM, Hans de Goede wrote:
Hi,
On 23-09-15 19:10, Bin Liu wrote:
> Hi,
>
> On 09/22/2015 04:18
Gregory CLEMENT writes:
> Hi Felipe,
>
> On ven., août 21 2015, Gregory CLEMENT
> wrote:
>>> According to the OTG specification after a timeout of
>>> OTG_TIME_A_WAIT_VRISE (the maximum value is 100ms) the driver must
Hi,
On 10/05/2015 02:54 PM, Felipe Balbi wrote:
Bin Liu writes:
Hi Felipe,
On 09/24/2015 03:37 AM, Hans de Goede wrote:
Hi,
On 23-09-15 22:59, Bin Liu wrote:
Hi,
On 09/23/2015 02:53 PM, Hans de Goede wrote:
Hi,
On 23-09-15 19:10, Bin Liu wrote:
Hi,
On 09/22/2015 04:18
This ID is for the Synopsys DWC_usb3 core with AXI interface on PCIe
HAPS platform. This core has the debug registers mapped at a separate
BAR in order to support enhanced hibernation.
Cc: # v3.18+
Signed-off-by: John Youn
---
This patch allows the dwc3 driver to run on the new Synopsys USB 3.1
IP core, albeit in USB 3.0 mode only.
The Synopsys USB 3.1 IP (DWC_usb31) retains mostly the same register
interface and programming model as the existing USB 3.0 controller IP
(DWC_usb3). However the GSNPSID and version numbers
Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls
whether the PHY receives the suspend signal from the controller.
Cc: # v3.18+
Signed-off-by: John Youn
---
Documentation/devicetree/bindings/usb/dwc3.txt | 2 ++
On Mon, 5 Oct 2015, Felipe Balbi wrote:
> Ramneek Mehresh writes:
>
> > Add support for otg for all freescale socs having internal
> > usb phy.
> >
> > Ramneek Mehresh (7):
> > usb:fsl:otg: Make fsl otg driver as tristate
> > usb:fsl:otg: Add controller
Hi Shawn,
Regarding below patch, Felipe has suggested to talk to you:
> [PATCH 3/3][v4] arm: dts: ls1021a: Add quirk for Erratum A009116
talk to you ARM-SoC maintainer.
https://lkml.org/lkml/2015/9/4/7
Please provide your comments. Inform me in case, if a resend is required.
Best Regards,
On Tue, Oct 6, 2015 at 4:59 AM, Felipe Balbi wrote:
> Vaishali Thakkar writes:
>
>> On Mon, Aug 24, 2015 at 2:29 PM, David Laight
>> wrote:
>>> From: Vaishali Thakkar [mailto:vthakkar1...@gmail.com]
Sent: 22 August 2015 02:57
On Mon, Oct 5, 2015 at 10:57 AM, Jayan John wrote:
> We are developing a custom USB device on a iMX6q platform with a Chipidea
> HDRC. The device uses a single NCM interface for communication with another
> OTG device i.e. Chipidea HDRC again. I see very poor iperf UDP
On Thu, Aug 27, 2015 at 1:43 PM, Ramneek Mehresh
wrote:
> Add support for otg for all freescale socs having internal
> usb phy.
>
> Ramneek Mehresh (7):
> usb:fsl:otg: Make fsl otg driver as tristate
> usb:fsl:otg: Add controller version based ULPI and UTMI phy
On Mon, 5 Oct 2015, Paul Jones wrote:
> > Increasing the max_sectors_kb value, on the other hand, might remove
> > overhead by allowing a higher percentage of the transfer to consist of
> > real data as opposed to CBW and CSW packets. This depends to some
> > extent on other factors (such as
On Mon, Oct 05, 2015 at 02:33:56PM -0500, Felipe Balbi wrote:
>
> IIRC we had this dependency because OTG needs support USB bus suspend
> and afaict, that's only available on PM builds
>
> --
> balbi
Hmm, our use case is separate device and host controllers on a Bay Trail
system. We don't
On Mon, 5 Oct 2015, Paul Jones wrote:
> >> Any ideas why the driver is requesting varying block sizes?
> >
> > The usb-storage driver requests what the block layer tells it to
> > request.
> I’m running a dd with a block size of 64k, so it seems to be
> aggregating 2 requests and then splits
On 5 October 2015 at 16:45, Tomeu Vizoso wrote:
> Hi,
>
> this is v9 of an attempt to make it easier for devices to remain in
> runtime PM when the system goes to sleep, mainly to reduce the time
> spent resuming devices.
>
> For this, we interpret the absence of all
On Sat, 3 Oct 2015 15:32:36 +0200 Christoph Hellwig wrote:
> This series consolidates the code to implement configfs attributes
> by providing the ->show and ->store method in common code and using
> container_of in the methods to access the containing structure.
>
> This reduces
On 10/1/2015 1:50 PM, Doug Anderson wrote:
> John,
>
> On Tue, Aug 18, 2015 at 5:19 PM, John Youn wrote:
>> Hi Yunzhi,
>>
>> My concern is with the delays due to calling the dwc2_core_reset
>> during probe. You could factor out the assertion of the core
>> soft reset from
> > Observations:
> >
> > - independent of activity/workload
>
> Are you sure about that? In your Intel pcap file, the problem occurred
> only after long periods of inactivity: 40 seconds the first time, 150
> seconds the second time.
Yes, because it can disconnect any time. Last time it
On Tue, Oct 6, 2015 at 3:38 AM, Fabio Estevam wrote:
> On Mon, Oct 5, 2015 at 10:57 AM, Jayan John wrote:
>> We are developing a custom USB device on a iMX6q platform with a Chipidea
>> HDRC. The device uses a single NCM interface for communication with
On 05 Oct 2015, at 20:54, Alan Stern wrote:
> On Mon, 5 Oct 2015, Paul Jones wrote:
>
>>> g_mass_storage, by default, uses 2 struct usb_request, try increasing that
>>> to 4
>>> (can be done from make menuconfig itself) and see if anything changes.
>> If you are
Certain Synopsys prototyping PHY boards are not able to meet timings
constraints for LPM. This allows the PHY to meet those timings by
leaving the PHY clock running during suspend.
Cc: # v3.18+
Signed-off-by: John Youn
---
Fix the alignment of the PCI device definitions. Also change the hex
digit capitalization of one constant to make it consistent with the
rest of the file and driver.
Signed-off-by: John Youn
---
drivers/usb/dwc3/dwc3-pci.c | 16
1 file changed, 8
Hi Shimoda-san,
On Mon, Oct 5, 2015 at 2:06 PM, Yoshihiro Shimoda
wrote:
> +bool xhci_rcar_is_compatible(struct usb_hcd *hcd)
> +{
> + struct device_node *of_node = hcd->self.controller->of_node;
> +
> + if (of_device_is_compatible(of_node,
On 10/2/2015 12:45 AM, Marek Szyprowski wrote:
> DWC2 module on some platforms needs three additional hardware
> resources: phy controller, clock and power supply. All of them must be
> enabled/activated to properly initialize and operate. This was initially
> handled in s3c-hsotg driver, which
On Mon, 5 Oct 2015, Alan Stern wrote:
> On Mon, 5 Oct 2015, Paul Jones wrote:
>
>>> Increasing the max_sectors_kb value, on the other hand, might remove
>>> overhead by allowing a higher percentage of the transfer to consist of
>>> real data as opposed to CBW and CSW packets. This depends to some
Vaishali Thakkar writes:
> On Mon, Aug 24, 2015 at 2:29 PM, David Laight wrote:
>> From: Vaishali Thakkar [mailto:vthakkar1...@gmail.com]
>>> Sent: 22 August 2015 02:57
>> ...
>>> >> - .bcdADC = __constant_cpu_to_le16(0x0100),
Hi Paul,
Good to see you're still hanging around.
On 10/5/2015 3:38 PM, Paul Zimmerman wrote:
> On Mon, 5 Oct 2015, Alan Stern wrote:
>> On Mon, 5 Oct 2015, Paul Jones wrote:
>>
Increasing the max_sectors_kb value, on the other hand, might remove
overhead by allowing a higher
John Youn writes:
Hi,
> On 10/2/2015 12:45 AM, Marek Szyprowski wrote:
>> DWC2 module on some platforms needs three additional hardware
>> resources: phy controller, clock and power supply. All of them must be
>> enabled/activated to properly initialize and operate. This
On Sat, 2015-10-03 at 17:19 +0200, Christoph Hellwig wrote:
> This ensures the dma mask that is supported by the driver is recorded
> in the device structure.
>
> Signed-off-by: Christoph Hellwig
> ---
> drivers/net/ethernet/amd/pcnet32.c | 2 +-
> 1 file changed, 1 insertion(+), 1
This patch set adds support for R-Car M2-N (r8a7793) and H3 (r8a7795) xHCI
controllers. To add support these new SoCs, this patch set modify some codes.
This patch is based on the latest usb.git / usb-next branch.
(The commit id = 07294cc2ea3000da706fd88c8ec7dcfadc715e14.)
Yoshihiro Shimoda (4):
This patch adds a firmware for the USB 3.0 host controllers of Renesas
R-Car H3 SoC.
This firmware is possible to use on R-Car H2 and M2. However, this
version causes performance degradation on R-Car H2 and M2. So, we would
like to keep the v1 firmware.
Signed-off-by: Yoshihiro Shimoda
This patch adds support for R-Car M2-N (r8a7793) xHCI controller.
This SoC is compatible with R-Car H2 (r8a7790) and R-Car M2-W (r8a7791).
Signed-off-by: Yoshihiro Shimoda
---
Documentation/devicetree/bindings/usb/usb-xhci.txt | 4 ++--
To add support for other SoCs in the future, this patch adds
xhci_rcar_is_compatible() to check the compatible string.
Signed-off-by: Yoshihiro Shimoda
---
drivers/usb/host/xhci-plat.c | 9 ++---
drivers/usb/host/xhci-rcar.c | 12
Hello.
On 10/5/2015 6:16 AM, Greg KH wrote:
Fix using the PCI_DEVICE() macro instead of less verbose PCI_VDEVICE().
Why?
Seemed a good idea to me back in March. :-)
I hate PCI_VDEVICE(), it's impossible to grep for things and does
Didn't think about grepping...
not help with
From: "David B. Robins"
Date: Wed, 30 Sep 2015 16:20:04 -0400
> If asix_rx_fixup_internal() fails to allocate rx->ax_skb, it will return
> but not clear rx->size. rx points to driver private data. A later call
> assumes that nonzero size means ax_skb was allocated and
The R-Car H3 has two xHCI controllers. This SoC is compatible with
R-Car Gen2 SoCs, however this SoC doesn't need some specific registers
setting, and need a new firmware.
Signed-off-by: Yoshihiro Shimoda
---
Documentation/devicetree/bindings/usb/usb-xhci.txt |
This patch changes code to ease the addition of next generation SoCs.
Signed-off-by: Yoshihiro Shimoda
---
drivers/usb/host/xhci-rcar.c | 51 +++-
1 file changed, 36 insertions(+), 15 deletions(-)
diff --git
From: Dean Jenkins
Date: Fri, 2 Oct 2015 14:29:03 +0100
> The ASIX RX handler algorithm is weak on error handling.
> There is a design flaw in the ASIX RX handler algorithm because the
> implementation for handling RX Ethernet frames for the DUB-E100 C1 can
> have
On 2015-10-05 06:31, David Miller wrote:
From: "David B. Robins"
Date: Wed, 30 Sep 2015 16:20:04 -0400
If asix_rx_fixup_internal() fails to allocate rx->ax_skb, it will
return
but not clear rx->size. rx points to driver private data. A later call
assumes that nonzero
We are developing a custom USB device on a iMX6q platform with a Chipidea
HDRC. The device uses a single NCM interface for communication with another
OTG device i.e. Chipidea HDRC again. I see very poor iperf UDP performance
after role reversal with iperf server running on gadget.
Kernel: 3.10.17
On Sat, 3 Oct 2015, Luis de Bethencourt wrote:
> > But I am not really sure where you are seeing the bug (mapping to
> > -EPERM) in this case? I think the only caller of hiddev_connect()
> > should be hid_connect(), and the only thing that guy cares about
> > whether individual callbacks
On 03/10/15 16:19, Christoph Hellwig wrote:
dma_set_mask already checks for a supported DMA mask before updating it,
the call to dma_supported is redundant.
Signed-off-by: Christoph Hellwig
Acked-by: Bert Kenward
The information contained in this
Have dev_pm_ops.prepare return 1 for USB devices and ports so that USB
devices can remain runtime-suspended when the system goes to a sleep
state, if their wakeup state is correct and they have runtime PM enabled.
Signed-off-by: Tomeu Vizoso
---
On Sun, Oct 04, 2015 at 11:55:06PM +0100, Mark Brown wrote:
> On Fri, Oct 02, 2015 at 02:11:25PM -0500, Felipe Balbi wrote:
> > On Fri, Oct 02, 2015 at 07:49:09PM +0100, Mark Brown wrote:
> > > On Fri, Oct 02, 2015 at 12:23:11PM -0500, Felipe Balbi wrote:
>
> > > > > Things more difficult, if
Hi,
this is v9 of an attempt to make it easier for devices to remain in
runtime PM when the system goes to sleep, mainly to reduce the time
spent resuming devices.
For this, we interpret the absence of all PM callback implementations as
it being safe to do direct_complete, so their ancestors
On Mon, Oct 05, 2015 at 10:15:11AM -0500, Felipe Balbi wrote:
> On Sun, Oct 04, 2015 at 11:55:06PM +0100, Mark Brown wrote:
> > The trouble is getting traction on adoption. Vendors have a habit of doing
> > things like finding problems and rather than reporting them deciding that
> > the
> >
Hi,
On Mon, Oct 05, 2015 at 05:18:33PM +0100, Mark Brown wrote:
> On Mon, Oct 05, 2015 at 10:15:11AM -0500, Felipe Balbi wrote:
> > On Sun, Oct 04, 2015 at 11:55:06PM +0100, Mark Brown wrote:
>
> > > The trouble is getting traction on adoption. Vendors have a habit of
> > > doing
> > > things
Hello,
in xHCI mode I'm experiencing random disconnects and reconnects of my ASMedia
ASM1051-based external HDD enclosure.
The only combination where the disconnects are happening is Intel USB Host
Controller + Linux kernel + XHCI mode (see further observations below).
I did some tracing with
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