If dwc3_core_init_mode() fails with deferred probe,
next probe fails on sysfs with
sysfs: cannot create duplicate filename
'/devices/pci:00/:00:11.0/dwc3.0.auto/dwc3.0.auto.ulpi'
To avoid this failure, clean up ULPI device.
Signed-off-by: Andy Shevchenko
---
drivers/usb/dwc3/core.c |
Hi,
On Fri, Aug 03, 2018 at 09:03:36AM +, Alexey Spirkov wrote:
> Existing code is not applicable to big-endian machines
> ctrlrequest fields received in USB endian - i.e. in little-endian
> and should be converted to cpu endianness before usage.
>
> Signed-off-by: Alexey Spirkov
> ---
>
Hi,
On Mon, Aug 27, 2018 at 12:57:55AM +, Takashi Matsuzawa wrote:
> Thank you for your suggestion.
> Yes, I am aware that full-OTG support code is being wiped out of the
> latest mainline kernels.
Okay. Let me know if reverting that patch can magically make HNP works.
> I am trying this
Hi Ajay,
I love your patch! Yet something to improve:
[auto build test ERROR on wsa/i2c/for-next]
[also build test ERROR on v4.19-rc1 next-20180827]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux
Hi Felipe,
On Tue, Aug 07, 2018 at 08:48:53PM +0200, Eugeniu Rosca wrote:
> Hello Felipe,
>
> On Fri, Jul 27, 2018 at 08:57:29PM +0200, Eugeniu Rosca wrote:
> > Hi Felipe,
> >
> > On Thu, Jul 26, 2018 at 01:51:35PM +0300, Felipe Balbi wrote:
> > > Eugeniu Rosca writes:
> > >
> > > > From:
On Mon, Aug 27, 2018 at 12:33 PM Loic Poulain wrote:
>
> Some hardware implementations require to configure pins differently
> according to the USB role (host/device), this can be an update of the
> pins routing or a simple GPIO value change.
>
> This patch introduces new optional "host" and
Hi Ajay,
On Fri, Aug 24, 2018 at 02:33:36PM -0700, Ajay Gupta wrote:
> Latest NVIDIA GPU cards have a Cypress CCGx Type-C controller
> over I2C interface.
>
> This UCSI I2C driver uses I2C bus driver interface for communicating
> with Type-C controller.
Cool. The patch looks fairly good to me,
Some hardware implementations require to configure pins differently
according to the USB role (host/device), this can be an update of the
pins routing or a simple GPIO value change.
This patch introduces new optional "host" and "device" pinctrls.
If these pinctrls are defined by the device, they
At OTG work running time, it's possible that several events need to be
addressed (e.g. ID and VBUS events). The current implementation handles
only one event at a time which leads to ignoring the other one. Fix it.
Signed-off-by: Loic Poulain
---
v2: no change
drivers/usb/chipidea/otg.c | 9
Phy power on/off cycle can happen several times during device life.
We then need to balance the extcon notifier registration accordingly.
Fixes: f0b5c2c96370 ("phy: qcom-usb-hs: Replace the extcon API")
Signed-off-by: Loic Poulain
---
v2: don't use devres version (power-on always followed by
The ChipIdea IRQ is disabled before scheduling the otg work and
re-enabled on otg work completion. However if the job is already
scheduled we have to undo the effect of disable_irq int order to
balance the IRQ disable-depth value.
Fixes: be6b0c1bd0be ("usb: chipidea: using one inline function to
Add compatibility for extcon-usb-gpio which can handle more
than one cable per instance, allowing coherency of USB cable
states (USB/USB-HOST). These states can be generated from ID
or/and VBUS pins.
In case only one extcon device is associated to the USB device,
and this device supports USB and
The Dragonboard-410c is able to act either as USB Host or Device.
The role can be determined at runtime via the USB_HS_ID pin which is
derived from the micro-usb port VBUS pin.
In Host role, SoC USB D+/D- are routed to the onboard USB 2.0 HUB.
In Device role, SoC USB D+/D- are routed to the USB
Some hardware implementations require to configure pins differently
according to the USB role (host/device), this can be an update of the
pins routing or a simple GPIO value change.
This patch introduces new optional "host" and "device" pinctrls.
If these pinctrls are defined by the device, they
On Fri, Aug 24, 2018 at 02:33:35PM -0700, Ajay Gupta wrote:
> Latest NVIDIA GPU card has USB Type-C interface. There is a
> Type-C controller which can be accessed over I2C.
>
> This driver add I2C bus driver to communicate with Type-C controller.
> I2C client driver will be part of USB Type-C
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