Re: USB CDP (charging downstream port) charging over Chipidea HDRC in host mode

2017-05-11 Thread Jayan John
On Tue, May 9, 2017 at 3:39 PM, Jayan John <jayanjoh...@gmail.com> wrote: > On Tue, May 9, 2017 at 1:10 PM, Peter Chen <hzpeterc...@gmail.com> wrote: >> On Tue, May 09, 2017 at 12:51:53PM +0530, Jayan John wrote: >>> On Tue, May 9, 2017 at 6:24 AM, Peter Chen

Re: USB CDP (charging downstream port) charging over Chipidea HDRC in host mode

2017-05-09 Thread Jayan John
On Tue, May 9, 2017 at 1:10 PM, Peter Chen <hzpeterc...@gmail.com> wrote: > On Tue, May 09, 2017 at 12:51:53PM +0530, Jayan John wrote: >> On Tue, May 9, 2017 at 6:24 AM, Peter Chen <hzpeterc...@gmail.com> wrote: >> > On Fri, May 05, 2017 at 10:40:01AM +0530, Jayan

Re: USB CDP (charging downstream port) charging over Chipidea HDRC in host mode

2017-05-09 Thread Jayan John
On Tue, May 9, 2017 at 6:24 AM, Peter Chen <hzpeterc...@gmail.com> wrote: > On Fri, May 05, 2017 at 10:40:01AM +0530, Jayan John wrote: >> I would like to add CDP (charging downstream port) capability over my >> OTG port in host mode. I am using an iMX6q platform with Chipid

USB CDP (charging downstream port) charging over Chipidea HDRC in host mode

2017-05-04 Thread Jayan John
I would like to add CDP (charging downstream port) capability over my OTG port in host mode. I am using an iMX6q platform with Chipidea HDRC (highspeed dual role controller) with 4.1 kernel. Looked at a bunch of documents like USB Battery Charging Specification and USB Power Delivery

Re: iperf UDP packet loss with Chipidea HDRC

2015-10-08 Thread Jayan John
On Thu, Oct 8, 2015 at 1:37 PM, Peter Chen <peter.c...@freescale.com> wrote: > On Mon, Oct 05, 2015 at 07:27:23PM +0530, Jayan John wrote: >> We are developing a custom USB device on a iMX6q platform with a Chipidea >> HDRC. The device uses a single NCM interface for commu

Re: iperf UDP packet loss with Chipidea HDRC

2015-10-06 Thread Jayan John
On Tue, Oct 6, 2015 at 1:31 PM, Greg KH <gre...@linuxfoundation.org> wrote: > On Tue, Oct 06, 2015 at 06:07:50AM +0530, Jayan John wrote: >> On Tue, Oct 6, 2015 at 3:38 AM, Fabio Estevam <feste...@gmail.com> wrote: >> > On Mon, Oct 5, 2015 at 10:57 AM, Jayan John

Re: iperf UDP packet loss with Chipidea HDRC

2015-10-05 Thread Jayan John
On Tue, Oct 6, 2015 at 3:38 AM, Fabio Estevam <feste...@gmail.com> wrote: > On Mon, Oct 5, 2015 at 10:57 AM, Jayan John <jayanjoh...@gmail.com> wrote: >> We are developing a custom USB device on a iMX6q platform with a Chipidea >> HDRC. The device uses a single NCM

iperf UDP packet loss with Chipidea HDRC

2015-10-05 Thread Jayan John
We are developing a custom USB device on a iMX6q platform with a Chipidea HDRC. The device uses a single NCM interface for communication with another OTG device i.e. Chipidea HDRC again. I see very poor iperf UDP performance after role reversal with iperf server running on gadget. Kernel: 3.10.17

Re: 64 byte EP0 OUT data transfer issue on Chipidea highspeed dual role controller

2015-07-01 Thread Jayan John
On Tue, Jun 30, 2015 at 8:23 AM, Jayan John jayanjoh...@gmail.com wrote: On Tue, Jun 30, 2015 at 6:50 AM, Peter Chen peter.c...@freescale.com wrote: On Tue, Jun 30, 2015 at 12:33 AM, Steve Calfee stevecal...@gmail.com wrote: On Mon, Jun 29, 2015 at 7:16 AM, Alan Stern st

Re: 64 byte EP0 OUT data transfer issue on Chipidea highspeed dual role controller

2015-06-29 Thread Jayan John
On Tue, Jun 30, 2015 at 6:50 AM, Peter Chen peter.c...@freescale.com wrote: On Tue, Jun 30, 2015 at 12:33 AM, Steve Calfee stevecal...@gmail.com wrote: On Mon, Jun 29, 2015 at 7:16 AM, Alan Stern st...@rowland.harvard.edu wrote: On Mon, 29 Jun 2015, Peter Chen wrote: Just like Steve

Re: 64 byte EP0 OUT data transfer issue on Chipidea highspeed dual role controller

2015-06-29 Thread Jayan John
On Tue, Jun 30, 2015 at 12:33 AM, Steve Calfee stevecal...@gmail.com wrote: On Mon, Jun 29, 2015 at 7:16 AM, Alan Stern st...@rowland.harvard.edu wrote: On Mon, 29 Jun 2015, Peter Chen wrote: Just like Steve pointed, it should be a ZLT problem, do you have below patch in your tree, and the

Re: 64 byte EP0 OUT data transfer issue on Chipidea highspeed dual role controller

2015-06-27 Thread Jayan John
On Sun, Jun 28, 2015 at 5:34 AM, Alan Stern st...@rowland.harvard.edu wrote: On Sat, 27 Jun 2015, Jayan John wrote: Thanks. Yes, the wLength value in the Setup packet is equal to 64. Aligned was the wrong term, multiple of 64 would be more appropriate :). The hid gadget driver queues

Re: 64 byte EP0 OUT data transfer issue on Chipidea highspeed dual role controller

2015-06-26 Thread Jayan John
On Fri, Jun 26, 2015 at 8:44 PM, David Laight david.lai...@aculab.com wrote: From: Steve Calfee Sent: 26 June 2015 15:59 On the host (Wandboard iMX6q) the test app opens /dev/hidraw0 and write 64 bytes with report ID (1). The HID device has no Interrupt OUT ep, therefore uses control

Re: 64 byte EP0 OUT data transfer issue on Chipidea highspeed dual role controller

2015-06-26 Thread Jayan John
On Sat, Jun 27, 2015 at 2:21 AM, Alan Stern st...@rowland.harvard.edu wrote: On Sat, 27 Jun 2015, Jayan John wrote: On Fri, Jun 26, 2015 at 8:44 PM, David Laight david.lai...@aculab.com wrote: From: Steve Calfee Sent: 26 June 2015 15:59 On the host (Wandboard iMX6q) the test app opens

Re: 64 byte EP0 OUT data transfer issue on Chipidea highspeed dual role controller

2015-06-26 Thread Jayan John
is reproducible for all data transfers that aligns on 64 bytes** ~jayan On Fri, Jun 26, 2015 at 5:10 PM, Alexander Shishkin alexander.shish...@linux.intel.com wrote: Jayan John jayanjoh...@gmail.com writes: I am developing a custom USB device on a iMX6q platform (Wandboard) Chipidea HDRC (highspeed

64 byte EP0 OUT data transfer issue on Chipidea highspeed dual role controller

2015-06-25 Thread Jayan John
I am developing a custom USB device on a iMX6q platform (Wandboard) Chipidea HDRC (highspeed dual role controller). The HID interface consists of a single Interrupt IN ep and ep0. It is required to send HID reports from Host to Gadget over ep0 (with set_report cmd on hidraw interface) in OUT

Re: 64 byte EP0 OUT data transfer issue on Chipidea highspeed dual role controller

2015-06-25 Thread Jayan John
cc Alexander Thanks On Thu, Jun 25, 2015 at 7:41 PM, Jayan John jayanjoh...@gmail.com wrote: I am developing a custom USB device on a iMX6q platform (Wandboard) Chipidea HDRC (highspeed dual role controller). The HID interface consists of a single Interrupt IN ep and ep0. It is required