On Tue, Nov 01, 2016 at 01:18:17PM +0200, Felipe Balbi wrote:
>
> Hi,
>
> John Youn writes:
> John Youn writes:
> > Add interrupt moderation interval binding for dwc3.
> >
> > Signed-off-by: John Youn
>
On Fri, Oct 28, 2016 at 01:30:07PM +0300, Felipe Balbi wrote:
> Mark Rutland <mark.rutl...@arm.com> writes:
> > On Thu, Oct 27, 2016 at 02:08:25PM -0700, John Youn wrote:
> >> On 10/26/2016 3:57 AM, Mark Rutland wrote:
> >> > On Tue, Oct 25, 2016 at 12:42:46PM
On Thu, Oct 27, 2016 at 02:08:25PM -0700, John Youn wrote:
> On 10/26/2016 3:57 AM, Mark Rutland wrote:
> > On Tue, Oct 25, 2016 at 12:42:46PM -0700, John Youn wrote:
> >> Add interrupt moderation interval binding for dwc3.
> >> + - snps,imod_interval: the interrupt mod
On Tue, Oct 25, 2016 at 12:42:46PM -0700, John Youn wrote:
> Add interrupt moderation interval binding for dwc3.
>
> Signed-off-by: John Youn
> ---
> Documentation/devicetree/bindings/usb/dwc3.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git
Hi,
On Tue, Aug 02, 2016 at 04:31:54PM +0200, Fabien Lahoudere wrote:
> This driver copy the configuration of the controller EEPROM via i2c.
> Configuration information is available in Documentation/usb/usb251x.txt
>
> Signed-off-by: Fabien Lahoudere
> ---
>
On Mon, Jun 06, 2016 at 05:20:03PM +0800, Frank Wang wrote:
> Signed-off-by: Frank Wang
> ---
>
> Changes in v3:
> - Added 'clocks' and 'clock-names' optional properties.
> - Specified 'otg-port' and 'host-port' as the sub-node name.
>
> Changes in v2:
> - Changed
Hi,
Sorry for my late reply to a prior version of this series, but I still
have concerns with some of the properties.
I'll repeat those below.
On Fri, Jul 31, 2015 at 02:03:53PM +0100, Chunfeng Yun wrote:
add a DT binding documentation of xHCI host controller for the
MT8173 SoC from Mediatek.
Hi,
+ - mediatek,usb-wakeup: to access usb wakeup control register
What exactly does this property imply?
There are some control registers for usb wakeup which are put in another
module, here to get the node of that module, and then use regmap and
syscon to operate it.
Ok. You need
On Wed, Jul 22, 2015 at 03:05:42PM +0100, Chunfeng Yun wrote:
add a DT binding documentation of xHCI host controller for the
MT8173 SoC from Mediatek.
Signed-off-by: Chunfeng Yun chunfeng@mediatek.com
---
.../devicetree/bindings/usb/mt8173-xhci.txt| 50
++
uses the dma-names in the node of
renesas_usbhs yet.
Given that:
Acked-by: Mark Rutland mark.rutl...@arm.com
Thanks,
Mark.
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On Wed, Apr 08, 2015 at 11:42:24AM +0100, Yoshihiro Shimoda wrote:
Since the DT should describe the hardware (not the driver limitation),
This patch revises the binding document about the dma-names to change
simple numbering as ch%d instead of txn and rxn.
The naming given in this patch looks
On Tue, Feb 10, 2015 at 07:50:24AM +, Zhangfei Gao wrote:
Signed-off-by: Zhangfei Gao zhangfei@linaro.org
---
.../devicetree/bindings/usb/hi6220-usb.txt | 49
++
1 file changed, 49 insertions(+)
create mode 100644
On Tue, Sep 02, 2014 at 11:39:08AM +0100, Vivek Gautam wrote:
Hi,
On Fri, Aug 29, 2014 at 12:18 AM, Mark Rutland mark.rutl...@arm.com wrote:
On Thu, Aug 28, 2014 at 09:01:56AM +0100, Vivek Gautam wrote:
Exynos7 also has a separate special gate clock going to the IP
apart from the usual
On Thu, Aug 28, 2014 at 09:01:56AM +0100, Vivek Gautam wrote:
Exynos7 also has a separate special gate clock going to the IP
apart from the usual AHB clock. So add support for the same.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/usb/dwc3/dwc3-exynos.c | 16
On Thu, Aug 28, 2014 at 09:01:57AM +0100, Vivek Gautam wrote:
Exynos7 SoC has now separate gate control for 125MHz pipe3 phy
clock, as well as 60MHz utmi phy clock.
So get the same and control in the phy-exynos5-usbdrd driver.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
successfully, but instead of this bugfix they'll get a dev_warn().
Given the binding looks sane and doesn't unnecessarily break existing
DTBs, for patches 1-3:
Acked-by: Mark Rutland mark.rutl...@arm.com
Thanks,
Mark.
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On Tue, Jun 24, 2014 at 07:44:10AM +0100, sundeep subbaraya wrote:
Ping
Thanks,
Sundeep.B.S.
On Tue, Jun 10, 2014 at 5:34 PM, subbaraya.sundeep.bha...@xilinx.com wrote:
From: Subbaraya Sundeep Bhatta sbha...@xilinx.com
Add devicetree bindings for Xilinx axi udc driver.
On Sun, Jun 29, 2014 at 10:29:49AM +0100, Robert Jarzmik wrote:
Mark Rutland mark.rutl...@arm.com writes:
On Wed, Jun 25, 2014 at 08:54:01PM +0100, Robert Jarzmik wrote:
The name of the clock input doesn't make sense.
I don't understand. With [1] does it make any more sense
On Wed, Jun 25, 2014 at 08:54:01PM +0100, Robert Jarzmik wrote:
Mark Rutland mark.rutl...@arm.com writes:
On Sun, Jun 22, 2014 at 10:04:58AM +0100, Robert Jarzmik wrote:
index 79729a9..0e4863f 100644
--- a/Documentation/devicetree/bindings/usb/pxa-usb.txt
+++ b/Documentation/devicetree
On Sun, Jun 22, 2014 at 10:04:58AM +0100, Robert Jarzmik wrote:
Add documentation for device-tree binding of arm PXA 27x udc (usb
device) driver.
Signed-off-by: Robert Jarzmik robert.jarz...@free.fr
Cc: devicet...@vger.kernel.org
---
Since V1: change OF id mrvl,pxa27x_udc -
On Sun, Jun 22, 2014 at 10:04:57AM +0100, Robert Jarzmik wrote:
Add support for device-tree device discovery. If devicetree is not
provided, fallback to legacy platform data discovery.
Signed-off-by: Robert Jarzmik robert.jarz...@free.fr
Cc: devicet...@vger.kernel.org
---
Since V1:
On Thu, Feb 27, 2014 at 12:12:50AM +, Sergei Shtylyov wrote:
Add support of the device tree probing for the Renesas R-Car generation 2 SoCs
documenting the device tree binding as necessary.
Signed-off-by: Sergei Shtylyov sergei.shtyl...@cogentembedded.com
---
This patch is against the
On Thu, Feb 20, 2014 at 05:14:30AM +, Peter Chen wrote:
Add fsl,imx6q-usbphy for imx6dq and imx6dl, add
fsl,imx6sl-usbphy for imx6sl.
Signed-off-by: Peter Chen peter.c...@freescale.com
---
Documentation/devicetree/bindings/usb/mxs-phy.txt |3 ++-
1 files changed, 2 insertions(+),
On Thu, Feb 20, 2014 at 05:14:33AM +, Peter Chen wrote:
Add anatop phandle which is used to access anatop registers to
control PHY's power and other USB operations.
Signed-off-by: Peter Chen peter.c...@freescale.com
---
Documentation/devicetree/bindings/usb/mxs-phy.txt |2 ++
1
On Thu, Feb 20, 2014 at 05:14:39AM +, Peter Chen wrote:
When we need the PHY can be waken up by external signals,
we can call this API. Besides, we call mxs_phy_disconnect_line
at this API to close the connection between USB PHY and
controller, after that, the line state from controller is
On Fri, Feb 21, 2014 at 09:40:29AM +, Peter Chen wrote:
Required properties:
-- compatible: Should be fsl,imx23-usbphy
+- compatible: fsl,imx23-usbphy for imx23 and imx28, fsl,imx6q-
usbphy
+ for imx6dq and imx6dl, fsl,imx6sl-usbphy for imx6sl
Minor nit, but could we
On Fri, Feb 21, 2014 at 01:41:03PM +, Michal Simek wrote:
Hi Mark,
On 02/21/2014 01:04 PM, Mark Rutland wrote:
On Thu, Feb 20, 2014 at 06:23:13PM +, Felipe Balbi wrote:
Hi,
On Wed, Feb 19, 2014 at 03:10:45PM +0530, Subbaraya Sundeep Bhatta wrote:
This patch adds xilinx axi
On Fri, Feb 21, 2014 at 03:41:03PM +, Felipe Balbi wrote:
Hi,
On Fri, Feb 21, 2014 at 12:04:54PM +, Mark Rutland wrote:
+Example:
+ axi-usb2-device@42e0 {
+compatible = xlnx,axi-usb2-device-4.00
On Fri, Jan 24, 2014 at 09:28:44AM +, Ashutosh singh wrote:
This patch adds support for USB_OTG on Phytec phyFLEX-i.MX6 Quad module.
Signed-off-by: Ashutosh singh ashutos...@phytec.in
---
arch/arm/boot/dts/imx6q-phytec-pbab01.dts |4
arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
On Fri, Jan 24, 2014 at 12:15:08PM +, Fabio Estevam wrote:
Hi Mark,
On Fri, Jan 24, 2014 at 9:50 AM, Mark Rutland mark.rutl...@arm.com wrote:
+
+ regulators {
+ compatible = simple-bus;
This is _not_ a simple bus. It doesn't have the required ranges
property
On Wed, Jan 08, 2014 at 06:15:38AM +, Roger Quadros wrote:
The omap-usb-host driver expects the 60MHz functional clock
of the USB host module to be named as init_60m_fclk.
Add this information in the DT binding document.
CC: Lee Jones lee.jo...@linaro.org
CC: Samuel Ortiz
On Wed, Jan 08, 2014 at 01:23:04PM +, Andreas Larsson wrote:
On 2014-01-06 17:22, Mark Rutland wrote:
Hi,
Apologies for the late reply, I wasn't able to access my mail much over
the Christmas break.
The patch is already applied to both the next branch of Felipe Balbi's
usb/next
On Sun, Jan 05, 2014 at 11:04:39PM +, Hans de Goede wrote:
Add support for ohci-platform instantiation from devicetree, including
optionally getting clks and a phy from devicetree, and enabling / disabling
those on power_on / off.
This should allow using ohci-platform from devicetree in
Hi,
Apologies for the late reply, I wasn't able to access my mail much over
the Christmas break.
On Mon, Dec 23, 2013 at 08:25:49PM +, Andreas Larsson wrote:
This adds an UDC driver for GRUSBDC USB Device Controller cores available in
the
GRLIB VHDL IP core library. The driver only
On Mon, Nov 18, 2013 at 12:57:42PM +, Ivan T. Ivanov wrote:
Hi Mark,
On Fri, 2013-11-15 at 16:42 +, Mark Rutland wrote:
On Tue, Nov 12, 2013 at 02:51:47PM +, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
Allow support to use 2nd HSPHY with USB2 Core
On Wed, Dec 04, 2013 at 09:20:07AM +, dt.ta...@gmail.com wrote:
From: Daniel Tang dt.ta...@gmail.com
The SoC name was mistakenly used instead of the vendor name in the
device tree binding for nspire-usb.
This patch fixes this before the driver becomes widely adopted.
How widely
On Thu, Nov 14, 2013 at 02:09:46AM +, Fabio Estevam wrote:
From: Fabio Estevam fabio.este...@freescale.com
When using external USB PHY or USB hub, it is common that they require a clock
input.
Add a 'clk_phy' clock, so that it can be retrieved from the device tree and
enabled in the
On Thu, Nov 14, 2013 at 02:09:47AM +, Fabio Estevam wrote:
From: Fabio Estevam fabio.este...@freescale.com
Udoo board has USBH1 port connected to a USB2514 hub.
Add support for it.
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
arch/arm/boot/dts/imx6q-udoo.dts | 34
On Mon, Dec 02, 2013 at 07:05:19AM +, Chris Ruehl wrote:
usb: phy-generic: Add ULPI VBUS support
Some platforms need to set the VBUS parameters of the ULPI
like ISP1504 which interact with overcurrent protection and
power switch MIC2575. Therefore it requires to set
* DRVVBUS
*
On Tue, Nov 12, 2013 at 02:51:45PM +, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
Allows MSM OTG controller to be specified via device tree.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
Cc: devicet...@vger.kernel.org
---
On Tue, Nov 12, 2013 at 02:51:47PM +, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
Allow support to use 2nd HSPHY with USB2 Core.
Some platforms may have configuration to allow USB controller
work with any of the two HSPHYs present. By default driver
configures USB core
[...]
+ phy-sleep_a_clk = devm_clk_get(phy-dev, sleep_a);
What means the _a in clock name?
They are 2 PHY's on 8074 chip. This drivers is supposed to
operate on PHY 0, thus sleep_a. PHY 1 is using sleep_b. Take a look
here http://www.spinics.net/lists/arm-kernel/msg276945.html
When
On Mon, Sep 23, 2013 at 08:31:48PM +0100, Felipe Balbi wrote:
Hi,
On Tue, Aug 20, 2013 at 12:56:03PM +0300, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
MSM USB3.0 core wrapper consist of USB3.0 IP from Synopsys
(SNPS) and HS, SS PHY's control and configuration
On Wed, Sep 18, 2013 at 03:21:18PM +0100, Felipe Balbi wrote:
Hi,
On Wed, Aug 28, 2013 at 05:01:51PM +0100, Mark Rutland wrote:
So it's not physically possible for someone to just wire up a single phy
to the device, either USB2-only or USB3?
of course it is :-) In fact, TI has
Graphics specific attributes
- use power in mA not in mA/2 as specifed in the USB2.0 specification
- use usbX-phy instead of usbX_phy
- use dma-controller instead of dma
Cc: Rob Herring rob.herr...@calxeda.com
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Stephen
On Tue, Aug 27, 2013 at 07:53:29PM +0100, Felipe Balbi wrote:
Hi,
On Tue, Aug 13, 2013 at 02:34:10PM +0100, Mark Rutland wrote:
On Mon, Aug 12, 2013 at 07:05:53PM +0100, Felipe Balbi wrote:
On Fri, Aug 09, 2013 at 01:42:15PM -0500, Kumar Gala wrote:
On Aug 9, 2013, at 11:28 AM
On Mon, Aug 12, 2013 at 07:05:53PM +0100, Felipe Balbi wrote:
On Fri, Aug 09, 2013 at 01:42:15PM -0500, Kumar Gala wrote:
On Aug 9, 2013, at 11:28 AM, Mark Rutland wrote:
On Fri, Aug 09, 2013 at 04:40:32PM +0100, Kumar Gala wrote:
The binding spec wasn't clear that the order
[Adding Olof]
On Mon, Aug 12, 2013 at 10:51:36AM +0100, Mark Brown wrote:
On Sun, Aug 11, 2013 at 09:53:01PM -0400, Alan Stern wrote:
On Sun, 11 Aug 2013, Mark Brown wrote:
One example that's bugging me right now is that on the Insignal Arndale
platform there's a USB hub connected to
On Fri, Aug 09, 2013 at 04:40:32PM +0100, Kumar Gala wrote:
The binding spec wasn't clear that the order of the phandles in the
usb-phy array has meaning. Clarify this point in the binding that
it should be USB2-HS-PHY, USB3-SS-PHY.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
On Tue, Aug 06, 2013 at 03:36:33PM +0100, Ivan T. Ivanov wrote:
Hi,
On Tue, 2013-08-06 at 15:03 +0100, Mark Rutland wrote:
On Tue, Aug 06, 2013 at 12:53:10PM +0100, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
On Wed, Aug 07, 2013 at 06:06:05PM +0100, Julius Werner wrote:
This breaks compatibility, both for an old kernel and a new dt and a new
kernel with an old dt. Is anyone using these bindings?
They only affect Samsung SoCs and have only been upstream for half a
year, so I doubt it's heavily
On Tue, Aug 06, 2013 at 07:00:17PM +0100, Julius Werner wrote:
This patch simplifies the way the phy-samsung-usb code finds the correct
power management register to enable PHY clock gating. Previously, the
code would calculate the register address from a device tree supplied
base address and
On Tue, Aug 06, 2013 at 12:53:10PM +0100, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
.../devicetree/bindings/usb/msm-ssusb.txt | 49 +++
drivers/usb/phy/Kconfig| 11 +
On Tue, Aug 06, 2013 at 12:53:11PM +0100, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
What does the glue layer do? Is it an actual piece of hardware, or
just some platform-specific code?
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
Hello,
[...]
-static struct of_device_id spear_ehci_id_table[] = {
- { .compatible = st,spear600-ehci, },
+static struct of_device_id SPEAr_ehci_id_table[] = {
+ { .compatible = st,SPEAr600-ehci, },
{ },
};
This will break anyone using the documented binding, and
Hi,
I have a few comments on the devicetree binding and the way it's parsed.
I note many are similar to those I commented on for the mv_udc and ehci-mv
devicetree code.
On Wed, Feb 06, 2013 at 07:23:36AM +, Chao Xie wrote:
The PHY is seperated from usb controller.
The usb controller used
On Mon, Feb 04, 2013 at 03:58:55PM +, Roger Quadros wrote:
Allows the OMAP EHCI controller to be specified via device tree.
Signed-off-by: Roger Quadros rog...@ti.com
---
.../devicetree/bindings/usb/omap-ehci.txt | 34 ++
drivers/usb/host/ehci-omap.c
Hi,
I have a few comments on the binding and the way it's parsed.
On Mon, Feb 04, 2013 at 03:58:56PM +, Roger Quadros wrote:
Allows the OMAP HS USB host controller to be specified
via device tree.
CC: Samuel Ortiz sa...@linux.intel.com
Signed-off-by: Roger Quadros rog...@ti.com
---
[...]
+
+- single_ulpi_bypass: Must be present if the controller contains a single
+ ULPI bypass control bit. e.g. OMAP3 silicon = ES2.1
Again it would be nicer to have '-' rather than '_' here. It might be worth
prefixing this ti,.
Is prefixing with ti really required? how does
On Fri, Jan 25, 2013 at 02:13:54AM +, chao xie wrote:
2013/1/24 Mark Rutland mark.rutl...@arm.com:
Hello,
On Thu, Jan 24, 2013 at 06:38:48AM +, Chao Xie wrote:
In original driver, we have callbacks in platform data, and some
dynamically allocations variables in platform data
[...]
@@ -170,19 +202,36 @@ static int mv_ehci_probe(struct platform_device
*pdev)
}
platform_set_drvdata(pdev, ehci_mv);
- ehci_mv-pdata = pdata;
ehci_mv-hcd = hcd;
- ehci_mv-clknum = pdata-clknum;
- for (clk_i = 0; clk_i ehci_mv-clknum;
On Fri, Jan 25, 2013 at 10:23:57AM +, Kishon Vijay Abraham I wrote:
Added a new driver for the usb part of control module. This has an API
to power on the USB2 phy and an API to write to the mailbox depending on
whether MUSB has to act in host mode or in device mode.
Writing to control
[...]
+OMAP CONTROL USB
+
+Required properties:
+ - compatible: Should be ti,omap-control-usb
+ - reg : Address and length of the register set for the device. It
contains
+ the address of control_dev_conf and otghs_control or
phy_power_usb
Could you not use '-'
On Fri, Jan 25, 2013 at 02:59:28PM +, Felipe Balbi wrote:
Hi,
On Fri, Jan 25, 2013 at 12:29:43PM +, Mark Rutland wrote:
+ depending upon omap4 or omap5.
+ - reg-names: The names of the register addresses corresponding to
the registers
+ filled in reg
On Fri, Jan 25, 2013 at 04:23:46PM +, Felipe Balbi wrote:
Hi,
On Fri, Jan 25, 2013 at 04:14:02PM +, Mark Rutland wrote:
On Fri, Jan 25, 2013 at 02:59:28PM +, Felipe Balbi wrote:
Hi,
On Fri, Jan 25, 2013 at 12:29:43PM +, Mark Rutland wrote:
+ depending upon
Hello,
On Thu, Jan 24, 2013 at 06:38:48AM +, Chao Xie wrote:
In original driver, we have callbacks in platform data, and some
dynamically allocations variables in platform data.
Now, these blocks are removed, the device tree support is easier
now.
Please could you also add a binding
On Thu, Jan 24, 2013 at 06:38:50AM +, Chao Xie wrote:
All blocks are removed. Add the device tree support for ehci.
Similarly to the last two patches, could you please add a binding document?
Signed-off-by: Chao Xie chao@marvell.com
Acked-by: Alan Stern st...@rowland.harvard.edu
---
+struct usb_phy *devm_usb_get_phy_by_phandle(struct device *dev,
+ const char *phandle, u8 index)
+{
+ struct usb_phy *phy = NULL, **ptr;
+ unsigned long flags;
+ struct device_node *node;
+
+ if (!dev-of_node) {
+ dev_dbg(dev, device does not have a
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