patch, I can easily meet a Kernel panic issue
if connect a low-speed USB mouse with the max port of FE2.1
multi-tt hub (1a40:0201) on rk3288 platform.
Signed-off-by: William Wu <william...@rock-chips.com>
---
drivers/usb/dwc2/hcd_queue.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
that according to usb 2.0 spec, the
maximum data payload size is 1023 bytes for each fs isoc ep,
and the maximum allowable interrupt data payload size is 64 bytes
or less for fs interrupt ep. So we set the size of object to be
1024 bytes in the kmem cache.
Signed-off-by: William Wu <william...
LIT IN transaction
- MDATA packet (176 bytes)
- CSPLIT IN transaction
- DATA0 packet (0 byte)
This patch use both the length of DATA0 and qtd->isoc_split_offset
to check if the DATA0 is in the second transaction.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v5:
- None
C
This patch fix dma unaligned problem and data lost problem for
isoc split in transfer.
Test on rk3288 platform, use an usb hs Hub (GL852G-12) and an usb
fs audio device (Plantronics headset) to capture and playback.
William Wu (2):
usb: dwc2: alloc dma aligned buffer for isoc split in
usb
This patch fix dma unaligned problem and data lost problem for
isoc split in transfer.
Test on rk3288 platform, use an usb hs Hub (GL852G-12) and an usb
fs audio device (Plantronics headset) to capture and playback.
William Wu (2):
usb: dwc2: alloc dma aligned buffer for isoc split in
usb
that according to usb 2.0 spec, the
maximum data payload size is 1023 bytes for each fs isoc ep,
and the maximum allowable interrupt data payload size is 64 bytes
or less for fs interrupt ep. So we set the size of object to be
1024 bytes in the kmem cache.
Signed-off-by: William Wu <william...@ro
LIT IN transaction
- MDATA packet (176 bytes)
- CSPLIT IN transaction
- DATA0 packet (0 byte)
This patch use both the length of DATA0 and qtd->isoc_split_offset
to check if the DATA0 is in the second transaction.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v4:
- None
C
that according to usb 2.0 spec, the
maximum data payload size is 1023 bytes for each fs isoc ep,
and the maximum allowable interrupt data payload size is 64 bytes
or less for fs interrupt ep. So we set the size of object to be
1024 bytes in the kmem cache.
Signed-off-by: William Wu <william...@ro
LIT IN transaction
- MDATA packet (176 bytes)
- CSPLIT IN transaction
- DATA0 packet (0 byte)
This patch use both the length of DATA0 and qtd->isoc_split_offset
to check if the DATA0 is in the second transaction.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v3:
-
This patch fix dma unaligned problem and data lost problem for
isoc split in transfer.
Test on rk3288 platform, use an usb hs Hub (GL852G-12) and an usb
fs audio device (Plantronics headset) to capture and playback.
William Wu (2):
usb: dwc2: alloc dma aligned buffer for isoc split in
usb
LIT IN transaction
- MDATA packet (176 bytes)
- CSPLIT IN transaction
- DATA0 packet (0 byte)
This patch use both the length of DATA0 and qtd->isoc_split_offset
to check if the DATA0 is in the second transaction.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v2:
- Modif
ned DMA for isoc split in.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v2:
- None
drivers/usb/dwc2/hcd.c | 63 +---
drivers/usb/dwc2/hcd.h | 10 +++
drivers/usb/dwc2/hcd_intr.c | 8 ++
drivers/usb/dwc2/hcd_
This patch fix dma unaligned problem and data lost problem for
isoc split in transfer.
Test on rk3288 platform, use an usb hs Hub (GL852G-12) and an usb
fs audio device (Plantronics headset) to capture and playback.
William Wu (2):
usb: dwc2: alloc dma aligned buffer for isoc split in
usb
LIT IN transaction
- MDATA packet (176 bytes)
- CSPLIT IN transaction
- DATA0 packet (0 byte)
This patch use both the length of DATA0 and qtd->isoc_split_offset
to check if the DATA0 is in the second transaction.
Signed-off-by: William Wu <william...@rock-chips.com>
---
drivers/usb/dwc2/hc
ned DMA for isoc split in.
Signed-off-by: William Wu <william...@rock-chips.com>
---
drivers/usb/dwc2/hcd.c | 63 +---
drivers/usb/dwc2/hcd.h | 10 +++
drivers/usb/dwc2/hcd_intr.c | 8 ++
drivers/usb/dwc2/hcd_queue.c | 8 +-
4
This patch fix dma unaligned problem and data lost problem for
isoc split in transfer.
Test on rk3288 platform, use an usb hs Hub (GL852G-12) and an usb
fs audio device (Plantronics headset) to capture and playback.
William Wu (2):
usb: dwc2: alloc dma aligned buffer for isoc split in
usb
fc
==
Disabling lock debugging due to kernel taint
android_work: sent uevent USB_STATE=CONFIGURED
This patch adds struct usb_endpoint_descriptor * -> u8 * type conversion
for ds variable, then we can get the correct address of comp_desc
with offset USB_DT_ENDPOINT_SIZE bytes.
Signed-off-by: W
register after powering on the PHYs.
Signed-off-by: William Wu <william...@rock-chips.com>
---
drivers/usb/dwc3/core.c | 46 ++
1 file changed, 22 insertions(+), 24 deletions(-)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index c
update the urb actual_length if the isoc frame
is valid.
Signed-off-by: William Wu <william...@rock-chips.com>
---
drivers/usb/dwc2/hcd_intr.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/usb/dwc2/hcd_intr.c b/drivers/usb/dwc2/hcd_intr.c
index 28a8210..01b1e13 100644
--- a/drive
-by: William Wu <william...@rock-chips.com>
---
drivers/usb/dwc2/hcd.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c
index 740c7e8..cc84f97 100644
--- a/drivers/usb/dwc2/hcd.c
+++ b/drivers/usb/dwc2/hcd.c
@@ -1
fc fc fc fc fc fc fc fc fc fc
ffc0601f6600: fc fc fc fc fc fc fc fc 00 00 00 00 00 00 00 00
==
Signed-off-by: William Wu <william...@rock-chips.com>
---
drivers/usb/gadget/function/f_fs.c | 10 +-
1 file c
from 566ns to 466ns, and fix the issue
that FS/LS devices not recognized if inserted through USB 3.0 HUB.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v3:
- change quirk name
- only read and write GUCTL1 if dwc3 version >= 2.50a
Changes in v2:
- fix cod
from 566ns to 466ns, and fix the issue
that FS/LS devices not recognized if inserted through USB 3.0 HUB.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v2:
- fix coding style
Documentation/devicetree/bindings/usb/dwc3.txt | 2 ++
drivers/usb/dwc3/
from 566ns to 466ns, and fix the issue
that FS/LS devices not recognized if inserted through USB 3.0 HUB.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Documentation/devicetree/bindings/usb/dwc3.txt | 2 ++
drivers/usb/dwc3/core.c| 14 ++
drive
From: William wu <william...@rock-chips.com>
The commit 4ac53087d6d4 ("usb: xhci: plat: Create both
HCDs before adding them") move add hcd to the end of
probe, this cause hcc_params uninitiated, because xHCI
driver sets hcc_params in xhci_gen_setup() called from
usb_add_hcd().
T
From: William wu <william...@rock-chips.com>
The commit 4ac53087d6d4 ("usb: xhci: plat: Create both
HCDs before adding them") move add hcd to the end of
probe, this cause hcc_params uninitiated, because xHCI
driver sets hcc_params in xhci_gen_setup() called from
usb_add_hcd().
T
From: William wu <w...@rock-chips.com>
On some platforms(e.g. rk3399 board), we can call hcd_add/remove
consecutively without calling usb_put_hcd/usb_create_hcd in between,
so hcd->flags can be stale.
If the HC dies due to whatever reason then without this patch we get
the below erro
From: William wu <w...@rock-chips.com>
On some platforms(e.g. rk3399 board), we can call hcd_add/remove
consecutively without calling usb_put_hcd/usb_create_hcd in between,
so hcd->flags can be stale.
If the HC dies due to whatever reason then without this patch we get
the below erro
This patch adds the devicetree documentation required for Rockchip
USB3.0 core wrapper consisting of USB3.0 IP from Synopsys.
It supports DRD mode, and could operate in device mode (SS, HS, FS)
and host mode (SS, HS, FS, LS).
Signed-off-by: William Wu <william...@rock-chips.com>
Acked-b
) and Peripheral
Only configurations.
The current driver supports Host only and Peripheral Only,
for now, and we can add support for DRD after dwc3 driver
adds generic handling of DRD.
William Wu (5):
usb: dwc3: of-simple: add compatible for rockchip rk3399
usb: dwc3: add dis_u2_freeclk_exists_quirk
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.
Signed-off-by: William Wu <william...@rock-chips.com>
Acked-by: Rob Herring <r...@kernel.org>
Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether disable delay PHY power change
from P0 to P1/P2/P3 when link state changing from U0
to U1/U2/U3 respectively.
Signed-off-by: William Wu <william...@rock-chips.com>
Acked-by: Rob Herring <r...@kernel.org>
configuration value is false, so we
need to reconfigure it by software.
Signed-off-by: William Wu <william...@rock-chips.com>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes in v11:
- None
Changes in v10:
- None
Changes in v9:
- None
Changes in v8:
- configure utmi interface via phy_t
Rockchip platform merely enable usb3 clocks and
populate its children. So we can use this generic
glue layer to support Rockchip dwc3.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v11:
- add compatible in dwc3-of-simple.c, and remove dwc3-rockchip.c (balbi)
Changes
This patch adds the devicetree documentation required for Rockchip
USB3.0 core wrapper consisting of USB3.0 IP from Synopsys.
It supports DRD mode, and could operate in device mode (SS, HS, FS)
and host mode (SS, HS, FS, LS).
Signed-off-by: William Wu <william...@rock-chips.com>
Acked-b
Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether disable delay PHY power change
from P0 to P1/P2/P3 when link state changing from U0
to U1/U2/U3 respectively.
Signed-off-by: William Wu <william...@rock-chips.com>
Acked-by: Rob Herring <r...@kernel.org>
configuration value is false, so we
need to reconfigure it by software.
Signed-off-by: William Wu <william...@rock-chips.com>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes in v10:
- None
Changes in v9:
- None
Changes in v8:
- configure utmi interface via phy_type property in DT (Heiko,
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.
Signed-off-by: William Wu <william...@rock-chips.com>
Acked-by: Rob Herring <r...@kernel.org>
than use the
generic of glue layer which merely enable some clocks
and populate its children.
William Wu (5):
usb: dwc3: add dis_u2_freeclk_exists_quirk
usb: dwc3: make usb2 phy utmi interface configurable
usb: dwc3: add dis_del_phy_power_chg_quirk
usb: dwc3: rockchip: add devicetree bindings
. And it need to reconfigure USB PHY interface of DWC3
core after deassert DWC3 controller reset.
The current driver supports Host only and Peripheral Only well, for
now, we will add support for OTG after we have it all stabilized.
Signed-off-by: William Wu <william...@rock-chips.com>
---
drive
This patch adds the devicetree documentation required for Rockchip
USB3.0 core wrapper consisting of USB3.0 IP from Synopsys.
It supports DRD mode, and could operate in device mode (SS, HS, FS)
and host mode (SS, HS, FS, LS).
Signed-off-by: William Wu <william...@rock-chips.com>
Acked-b
configuration value is false, so we
need to reconfigure it by software.
Signed-off-by: William Wu <william...@rock-chips.com>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes in v9:
- None
Changes in v8:
- configure utmi interface via phy_type property in DT (Heiko, Rob Herring)
- add A
Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether disable delay PHY power change
from P0 to P1/P2/P3 when link state changing from U0
to U1/U2/U3 respectively.
Signed-off-by: William Wu <william...@rock-chips.com>
Acked-by: Rob Herring <r...@kernel.org>
, but not use the
generic of glue layer which merely enable some clocks
and populate its children.
William Wu (5):
usb: dwc3: add dis_u2_freeclk_exists_quirk
usb: dwc3: make usb2 phy utmi interface configurable
usb: dwc3: add dis_del_phy_power_chg_quirk
usb: dwc3: rockchip: add devicetree bindings
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.
Signed-off-by: William Wu <william...@rock-chips.com>
Acked-by: Rob Herring <r...@kernel.org>
Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether disable delay PHY power change
from P0 to P1/P2/P3 when link state changing from U0
to U1/U2/U3 respectively.
Signed-off-by: William Wu <william...@rock-chips.com>
Acked-by: Rob Herring <r...@kernel.org>
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.
Signed-off-by: William Wu <william...@rock-chips.com>
Acked-by: Rob Herring <r...@kernel.org>
configuration value is false, so we
need to reconfigure it by software.
Signed-off-by: William Wu <william...@rock-chips.com>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes in v8:
- configure utmi interface via phy_type property in DT (Heiko, Rob Herring)
- add Acked-by (Rob Herring)
- m
This series add support for rockchip dwc3 driver,
and add additional optional properties for specific
platforms (e.g., rockchip rk3399 platform).
William Wu (5):
usb: dwc3: of-simple: add compatible for rockchip rk3399
usb: dwc3: add dis_u2_freeclk_exists_quirk
usb: dwc3: make usb2 phy utmi
Rockchip platform merely enable usb3 clocks and
populate its children. So we can use this generic
glue layer to support Rockchip dwc3.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v8:
- None
Changes in v7:
- None
Changes in v6:
- None
Changes in v5:
- change comp
This patch adds the devicetree documentation required for Rockchip
USB3.0 core wrapper consisting of USB3.0 IP from Synopsys.
It supports DRD mode, and could operate in device mode (SS, HS, FS)
and host mode (SS, HS, FS, LS).
Signed-off-by: William Wu <william...@rock-chips.com>
Acked-b
This patch adds the devicetree documentation required for Rockchip
USB3.0 core wrapper consisting of USB3.0 IP from Synopsys.
It supports DRD mode, and could operate in device mode (SS, HS, FS)
and host mode (SS, HS, FS, LS).
Signed-off-by: William Wu <william...@rock-chips.com>
Acked-b
Rockchip platform merely enable usb3 clocks and
populate its children. So we can use this generic
glue layer to support Rockchip dwc3.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v7:
- None
Changes in v6:
- None
Changes in v5:
- change compatible from "ro
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v7:
- None
Changes in v6:
Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether disable delay PHY power change
from P0 to P1/P2/P3 when link state changing from U0
to U1/U2/U3 respectively.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v7:
- None
Changes in v6:
), the
default PHYIF configuration value is fault, so we need to
reconfigure it by software.
And refer to the DWC3 databook, the GUSB2PHYCFG.USBTRDTIM
must be set to the corresponding value according to the
UTMI+ PHY interface.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes
This series add support for rockchip dwc3 driver,
and add additional optional properties for specific
platforms (e.g., rockchip rk3399 platform).
William Wu (5):
usb: dwc3: of-simple: add compatible for rockchip rk3399
usb: dwc3: add dis_u2_freeclk_exists_quirk
usb: dwc3: make usb2 phy utmi
This patch adds the devicetree documentation required for Rockchip
USB3.0 core wrapper consisting of USB3.0 IP from Synopsys.
It supports DRD mode, and could operate in device mode (SS, HS, FS)
and host mode (SS, HS, FS, LS).
Signed-off-by: William Wu <william...@rock-chips.com>
---
C
This series add support for rockchip dwc3 driver,
and add additional optional properties for specific
platforms (e.g., rockchip rk3399 platform).
William Wu (5):
usb: dwc3: of-simple: add compatible for rockchip rk3399
usb: dwc3: add dis_u2_freeclk_exists_quirk
usb: dwc3: add
Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether disable delay PHY power change
from P0 to P1/P2/P3 when link state changing from U0
to U1/U2/U3 respectively.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v6:
- use '-' instead of '_'
Rockchip platform merely enable usb3 clocks and
populate its children. So we can use this generic
glue layer to support Rockchip dwc3.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v6:
- None
Changes in v5:
- change compatible from "rockchip,dwc3" to "
configuration value is fault, so we need to
reconfigure it by software.
And refer to the dwc3 databook, the GUSB2PHYCFG.USBTRDTIM
must be set to the corresponding value according to
the UTMI+ PHY interface.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v6:
- use '-' i
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v6:
- use '-' instead of '_'
Dear Rob,
On 07/01/2016 10:38 AM, Rob Herring wrote:
On Thu, Jun 30, 2016 at 07:12:55PM +0800, William Wu wrote:
Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether disable delay PHY power change
from P0 to P1/P2/P3 when link state changing from U0
to U1/U2/U3
Dear Rob,
On 07/01/2016 10:32 AM, Rob Herring wrote:
On Thu, Jun 30, 2016 at 07:12:53PM +0800, William Wu wrote:
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input
Dear Heiko,
On 06/30/2016 08:15 PM, Heiko Stuebner wrote:
Hi William,
Am Donnerstag, 30. Juni 2016, 19:16:40 schrieb William Wu:
This patch adds the devicetree documentation required for Rockchip
USB3.0 core wrapper consisting of USB3.0 IP from Synopsys.
It supports DRD mode, and could
This patch adds the devicetree documentation required for Rockchip
USB3.0 core wrapper consisting of USB3.0 IP from Synopsys.
It supports DRD mode, and could operate in device mode (SS, HS, FS)
and host mode (SS, HS, FS, LS).
Signed-off-by: William Wu <william...@rock-chips.com>
---
C
This series add support for rockchip dwc3 driver,
and add additional optional properties for specific
platforms (e.g., rockchip rk3399 platform).
William Wu (5):
usb: dwc3: of-simple: add compatible for rockchip rk3399
usb: dwc3: add dis_u2_freeclk_exists_quirk
usb: dwc3: add
Rockchip platform merely enable usb3 clocks and
populate its children. So we can use this generic
glue layer to support Rockchip dwc3.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v5:
- change compatible from "rockchip,dwc3" to "rockchip,rk3399-dwc3&qu
Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether disable delay PHY power change
from P0 to P1/P2/P3 when link state changing from U0
to U1/U2/U3 respectively.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v5:
- None
Changes in v4:
-
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v5:
- None
Changes in v4:
-
configuration value is fault, so we need to
reconfigure it by software.
And refer to the dwc3 databook, the GUSB2PHYCFG.USBTRDTIM
must be set to the corresponding value according to
the UTMI+ PHY interface.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v5:
- None
Changes
Dear Heiko,
On 06/29/2016 12:41 AM, Heiko Stuebner wrote:
Hi William,
Am Dienstag, 28. Juni 2016, 11:18:04 schrieb William Wu:
So about the usb3 controller clk management, I think it should contain
the following clk:
1. aclk_usb3otg1
2. aclk_usb3otg0
3. aclk_usb3_grf
correct
Dear Heiko,
On 06/25/2016 03:50 AM, Heiko Stuebner wrote:
Hi William,
Am Dienstag, 21. Juni 2016, 17:11:44 schrieb William Wu:
On 06/20/2016 10:44 PM, Heiko Stübner wrote:
Am Freitag, 17. Juni 2016, 17:18:59 schrieb William Wu:
On 06/17/2016 07:15 AM, Heiko Stübner wrote:
Am Donnerstag, 2
Dear Heiko,
On 06/20/2016 10:44 PM, Heiko Stübner wrote:
Hi William,
Am Freitag, 17. Juni 2016, 17:18:59 schrieb William Wu:
On 06/17/2016 07:15 AM, Heiko Stübner wrote:
Am Donnerstag, 2. Juni 2016, 20:34:56 schrieb William Wu:
This patch adds the devicetree documentation required
Dear Heiko,
On 06/17/2016 07:15 AM, Heiko Stübner wrote:
Hi William,
Am Donnerstag, 2. Juni 2016, 20:34:56 schrieb William Wu:
This patch adds the devicetree documentation required for Rockchip
USB3.0 core wrapper consisting of USB3.0 IP from Synopsys.
It supports DRD mode, and could operate
configuration value is fault, so we need to
reconfigure it by software.
And refer to the dwc3 databook, the GUSB2PHYCFG.USBTRDTIM
must be set to the corresponding value according to
the UTMI+ PHY interface.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v4:
- rebase
This series add support for rockchip dwc3 driver,
and add additional optional properties for specific
platforms (e.g., rockchip rk3399 platform).
William Wu (5):
usb: dwc3: of-simple: add compatible for rockchip
usb: dwc3: add dis_u2_freeclk_exists_quirk
usb: dwc3: add phyif_utmi_quirk
Rockchip platform merely enable usb3 clocks and
populate its children. So we can use this generic
glue layer to support Rockchip dwc3.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v4:
- None
Changes in v3:
- None
Changes in v2:
- sort the list of_dwc3_simple_match
Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether disable delay PHY power change
from P0 to P1/P2/P3 when link state changing from U0
to U1/U2/U3 respectively.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v4:
- rebase on top of balbi t
This patch adds the devicetree documentation required for Rockchip
USB3.0 core wrapper consisting of USB3.0 IP from Synopsys.
It supports DRD mode, and could operate in device mode (SS, HS, FS)
and host mode (SS, HS, FS, LS).
Signed-off-by: William Wu <william...@rock-chips.com>
---
C
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v4:
- rebase on top of balbi t
Dear Sergei,
On 05/27/2016 07:54 PM, Sergei Shtylyov wrote:
Hello.
On 5/27/2016 2:31 PM, William Wu wrote:
This patch documents the device tree documentation required for
Documents the documentation? :-)
Ah, my commit log seems a little weird. I'll corrcet it next patch.
Thanks
This patch documents the device tree documentation required for
Rockchip USB3.0 core wrapper consist of USB3.0 IP from Synopsys.
It could operate in device mode (SS, HS, FS) and host
mode (SS, HS, FS, LS).
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v3:
- ad
This series add support for rockchip dwc3 driver,
and add additional optional properties for specific
platforms (e.g., rockchip platform).
William Wu (5):
usb: dwc3: of-simple: add compatible for rockchip
usb: dwc3: add dis_u2_freeclk_exists_quirk
usb: dwc3: add phyif_utmi_quirk
usb: dwc3
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v3:
- None
Changes in v2:
configuration value is fault, so we need to
reconfigure it by software.
And refer to the dwc3 databook, the GUSB2PHYCFG.USBTRDTIM
must be set to the corresponding value according to
the UTMI+ PHY interface.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v3:
- None
Changes
Rockchip platform merely enable usb3 clocks and
populate its children. So we can use this generic
glue layer to support Rockchip dwc3.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v3:
- None
Changes in v2:
- sort the list of_dwc3_simple_match (Doug)
drivers/us
Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether disable delay PHY power change
from P0 to P1/P2/P3 when link state changing from U0
to U1/U2/U3 respectively.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v3:
- None
Changes in v2:
Hi Felipe & Rob,
On 05/25/2016 04:04 PM, Felipe Balbi wrote:
Hi,
William Wu <william...@rock-chips.com> writes:
Hi Felipe,
On 05/24/2016 05:32 PM, Felipe Balbi wrote:
Hi,
William Wu <william...@rock-chips.com> writes:
This patch documents the device tree documentation requi
request correctly.
Signed-off-by: William Wu <william...@rock-chips.com>
---
drivers/usb/gadget/composite.c | 21 +
1 file changed, 13 insertions(+), 8 deletions(-)
diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c
index d67de0d..eb64848 100644
be reset to
default 0 after the core reset. Dump GUCTL1 reg from
debugfs is more convenient for us.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v2:
- add commit log
drivers/usb/dwc3/core.h| 1 +
drivers/usb/dwc3/debugfs.c | 1 +
2 files changed, 2 insertions(+)
diff
On 05/13/2016 06:05 PM, William Wu wrote:
GUCTL1 reg has some useful functions which can be
written by user. For rockchip platform, we set
GUCTL1.DEV_FORCE_20_CLK_FOR_30_CLK (bit26, applicable
for the core is programmed to operate in 2.0 device
only) to 1 in bootrom, and after start the kernel
be reset to
default 0 after the core reset. Dump GUCTL1 reg from
debugfs is more convenient for us.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v2:
- add commit log
drivers/usb/dwc3/core.h| 1 +
drivers/usb/dwc3/debugfs.c | 1 +
2 files changed, 2 insertions(+)
diff
This patch documents the device tree documentation required for
Rockchip USB3.0 core wrapper consist of USB3.0 IP from Synopsys.
It could operate in device mode (SS, HS, FS) and host
mode (SS, HS, FS, LS).
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v2:
- add ro
Dear Felipe,
On 05/13/2016 05:37 PM, Felipe Balbi wrote:
Hi,
William Wu <william...@rock-chips.com> writes:
This series add support for rockchip dwc3 driver,
and add additional optional properties for specific
platforms (e.g., rockchip platform).
William Wu (5):
usb: dwc3: of-simpl
Rockchip platform merely enable usb3 clocks and
populate its children. So we can use this generic
glue layer to support Rockchip dwc3.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v2:
- sort the list of_dwc3_simple_match (Doug)
drivers/usb/dwc3/dwc3-of-simple.c |
This series add support for rockchip dwc3 driver,
and add additional optional properties for specific
platforms (e.g., rockchip platform).
William Wu (5):
usb: dwc3: of-simple: add compatible for rockchip
usb: dwc3: add dis_u2_freeclk_exists_quirk
usb: dwc3: add phyif_utmi_quirk
usb: dwc3
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v2:
- None
Documentation/devi
Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether disable delay PHY power change
from P0 to P1/P2/P3 when link state changing from U0
to U1/U2/U3 respectively.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v2:
- None
Documentation/devi
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