Hi Peter,
On 13/07/15 13:20, Roger Quadros wrote:
On 13/07/15 05:14, Peter Chen wrote:
On Wed, Jul 08, 2015 at 01:19:33PM +0300, Roger Quadros wrote:
The OTG core instantiates the OTG Finite State Machine
per OTG controller and manages starting/stopping the
host and gadget controllers based
On Fri, Aug 14, 2015 at 12:42:38PM +0300, Roger Quadros wrote:
Hi Peter,
On 13/07/15 13:20, Roger Quadros wrote:
On 13/07/15 05:14, Peter Chen wrote:
On Wed, Jul 08, 2015 at 01:19:33PM +0300, Roger Quadros wrote:
The OTG core instantiates the OTG Finite State Machine
per OTG controller
Hi,
On 21/07/15 13:52, Li Jun wrote:
Hi,
[...]
+ otg_timer_init(A_WAIT_ENUM, otgd, set_tmout, TB_SRP_FAIL, NULL);
2 timers are missing: B_DATA_PLS, B_SSEND_SRP.
Those 2 are not used by usb-otg-fsm.c. We can add it when usb-otg-fsm.c is
updated.
ok.
+}
[...]
+
+/**
+
Hi,
[...]
+ otg_timer_init(A_WAIT_ENUM, otgd, set_tmout, TB_SRP_FAIL, NULL);
2 timers are missing: B_DATA_PLS, B_SSEND_SRP.
Those 2 are not used by usb-otg-fsm.c. We can add it when usb-otg-fsm.c is
updated.
ok.
+}
[...]
+
+/**
+ * OTG FSM ops function to start/stop
On Fri, Jul 17, 2015 at 03:06:18PM +0300, Roger Quadros wrote:
+
+/**
+ * OTG FSM ops function to start/stop host
+ */
+static int usb_otg_start_host(struct otg_fsm *fsm, int on)
+{
+ struct otg_data *otgd = container_of(fsm, struct otg_data, fsm);
+ struct otg_hcd_ops *hcd_ops;
Hi Li,
On 17/07/15 10:48, Li Jun wrote:
Hi, Roger
On Wed, Jul 08, 2015 at 01:19:33PM +0300, Roger Quadros wrote:
The OTG core instantiates the OTG Finite State Machine
per OTG controller and manages starting/stopping the
host and gadget controllers based on the bus state.
It provides
Hi, Roger
On Wed, Jul 08, 2015 at 01:19:33PM +0300, Roger Quadros wrote:
The OTG core instantiates the OTG Finite State Machine
per OTG controller and manages starting/stopping the
host and gadget controllers based on the bus state.
It provides APIs for the following tasks
- Registering
On 13/07/15 05:14, Peter Chen wrote:
On Wed, Jul 08, 2015 at 01:19:33PM +0300, Roger Quadros wrote:
The OTG core instantiates the OTG Finite State Machine
per OTG controller and manages starting/stopping the
host and gadget controllers based on the bus state.
It provides APIs for the
On Wed, Jul 08, 2015 at 01:19:33PM +0300, Roger Quadros wrote:
The OTG core instantiates the OTG Finite State Machine
per OTG controller and manages starting/stopping the
host and gadget controllers based on the bus state.
It provides APIs for the following tasks
- Registering an OTG
The OTG core instantiates the OTG Finite State Machine
per OTG controller and manages starting/stopping the
host and gadget controllers based on the bus state.
It provides APIs for the following tasks
- Registering an OTG capable controller
- Registering Host and Gadget controllers to OTG core
-
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