On 8/25/2016 3:01 AM, Heiko Stübner wrote:
> Hi John,
>
> Am Mittwoch, 24. August 2016, 16:20:01 schrieb John Youn:
>> When a force mode bit is set and the IDDIG debounce filter is enabled,
>> there is a delay for the forced mode to take effect. This delay is due
>> to the IDDIG debounce filter an
Hi John,
Am Mittwoch, 24. August 2016, 16:20:01 schrieb John Youn:
> When a force mode bit is set and the IDDIG debounce filter is enabled,
> there is a delay for the forced mode to take effect. This delay is due
> to the IDDIG debounce filter and is variable depending on the platform's
> PHY cloc
When a force mode bit is set and the IDDIG debounce filter is enabled,
there is a delay for the forced mode to take effect. This delay is due
to the IDDIG debounce filter and is variable depending on the platform's
PHY clock speed. To account for this delay we can poll for the expected
mode.
On a
