Hi,
Stefan Wahren writes:
> Hi John,
>
>> John Youn hat am 1. September 2016 um 23:07
>> geschrieben:
>>
>>
>> This series accounts for the delay from the IDDIG debounce filter when
>> switching modes. This delay is a function of the PHY clock
Hi John,
> John Youn hat am 1. September 2016 um 23:07
> geschrieben:
>
>
> This series accounts for the delay from the IDDIG debounce filter when
> switching modes. This delay is a function of the PHY clock speed and
> can range from 5-50 ms. This delay must be taken
This series accounts for the delay from the IDDIG debounce filter when
switching modes. This delay is a function of the PHY clock speed and
can range from 5-50 ms. This delay must be taken into account on core
reset and force modes. A full explanation is provided in the patch
commit log and code