On Fri, Mar 10, 2017 at 04:49:59AM +, Benson Liou wrote:
> Important Notice: This email message and any attachments thereto are
> confidential and/or privileged and/or subject to privacy laws and are
> intended only for use by the addressee(s) named above. If you are not the
> intended
On 10 March 2017 at 14:30, Jun Li wrote:
>> >> >
>> >> > Will generic phy need add extcon as well?
>> >>
>> >> Yes, will add a 'struct extcon_dev*' in 'struct usb_phy', which will
>> >> be common code.
>> >>
>> >
>> > I mean the common code need add 'struct extcon_dev' into both
> -Original Message-
> From: Baolin Wang [mailto:baolin.w...@linaro.org]
> Sent: Thursday, March 09, 2017 7:23 PM
> To: Jun Li
> Cc: NeilBrown ; Felipe Balbi ; Greg KH
> ; Sebastian Reichel ;
On Thu, Feb 16, 2017 at 10:18:58PM +0100, Uwe Kleine-König wrote:
> All currently supported i.MX25-based machines use phy_type = "utmi" and
> dr_mode = "otg". So this seems to be a sensible default.
>
> This also doesn't hurt out-of-tree machines because up to now they had
> to specify these two
Cleanly iounmap the pointer in error and exit paths.
Signed-off-by: Bin Liu
---
v2: use a meaningful goto label
drivers/usb/musb/musb_dsps.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/musb/musb_dsps.c b/drivers/usb/musb/musb_dsps.c
index
Hi,
I have encounter a problem while sending Serial_State packet of CDC-ACM
from Linux gadget to Linux host .
Here is my question:
The environment is a USB device which runs Linux is using CDC-ACM(f_acm.c)
to communicate with a Linux host(cdc-acm.c). When device tries to send
On 08/03/2017 16:17, Bjorn Helgaas wrote:
[snip excellent in-depth overview]
I think I'm making progress, in that I now have a better
idea of what I don't understand. So I'm able to ask
(hopefully) less vague questions.
Take the USB3 PCIe adapter I've been testing with. At some
point during
If you tell me how to do it, with pleasure. I have an EC21 on hand just not the
knowledge how to do it.
Thanks,
Bali
> On Mar 9, 2017, at 1:42 PM, Dan Williams wrote:
>
> On Thu, 2017-03-09 at 13:14 -0500, Balazs Harmath wrote:
>> So i can expect these to be added soon?
>
>
On Thu, 2017-03-09 at 13:14 -0500, Balazs Harmath wrote:
> So i can expect these to be added soon?
Are you able to apply and test this patch, and see if it works for your
device? That would help.
Thanks!
Dan
> Thanks,
> Bali
>
>
> > On Mar 9, 2017, at 12:32 PM, Dan Williams
On Thu, 9 Mar 2017, Gregory CLEMENT wrote:
> From: Hua Jing
>
> - Add a new compatible string for the Armada 3700 SoCs
>
> - add sbuscfg support for orion usb controller driver. For the SoCs
> without hlock, need to program BAWR/BARD/AHBBRST fields in the sbuscfg
>
So i can expect these to be added soon?
Thanks,
Bali
> On Mar 9, 2017, at 12:32 PM, Dan Williams wrote:
>
> Add Quectel UC15, UC20, EC21, and EC25. The EC20 is handled by
> qcserial due to a USB VID/PID conflict with an existing Acer
> device.
>
> Signed-off-by: Dan
Hi,
The EHCI controller in the Armada 37xx SoCs is the one used on many
other mvebu SoCs such as the orion5x, the kirkwood, or the
armada. However, for Armada 37xx an extra initialization step is
needed: this is the purpose of the first patch.
The second patch allows to build the driver for the
From: Hua Jing
- Add a new compatible string for the Armada 3700 SoCs
- add sbuscfg support for orion usb controller driver. For the SoCs
without hlock, need to program BAWR/BARD/AHBBRST fields in the sbuscfg
register to guarantee the AHB master's burst would not
Armada 37xx SoC embedded an EHCI controller. This patch adds the device
tree node enabling its support.
Reviewed-by: Andrew Lunn
Signed-off-by: Gregory CLEMENT
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 6 ++
The mvebu ARM64 SoCs no longer select PLAT_ORION. However Armada 37xx use
the Orion EHCI controller. This patch allows the Orion EHCI driver to be
built when ARCH_MVEBU is selected.
Reviewed-by: Andrew Lunn
Signed-off-by: Gregory CLEMENT
---
Hi,
The EHCI controller in the Armada 37xx SoCs is the one used on many
other mvebu SoCs such as the orion5x, the kirkwood, or the
armada. However, for Armada 37xx an extra initialization step is
needed: this is the purpose of the first patch.
The second patch allows to build the driver for the
Armada 37xx SoC embedded an EHCI controller. This patch adds the device
tree node enabling its support.
Reviewed-by: Andrew Lunn
Signed-off-by: Gregory CLEMENT
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 6 ++
From: Hua Jing
- Add a new compatible string for the Armada 3700 SoCs
- add sbuscfg support for orion usb controller driver. For the SoCs
without hlock, need to program BAWR/BARD/AHBBRST fields in the sbuscfg
register to guarantee the AHB master's burst would not
The mvebu ARM64 SoCs no longer select PLAT_ORION. However Armada 37xx use
the Orion EHCI controller. This patch allows the Orion EHCI driver to be
built when ARCH_MVEBU is selected.
Reviewed-by: Andrew Lunn
Signed-off-by: Gregory CLEMENT
---
Hi,
On jeu., mars 09 2017, Gregory CLEMENT
wrote:
> Hi,
>
> The EHCI controller in the Armada 37xx SoCs is the one used on many
> other mvebu SoCs such as the orion5x, the kirkwood, or the
> armada. However, for Armada 37xx an extra initialization step is
The local variable ept_cfg is not used anymore in usba_ep_enable.
Use ep->ept_cfg in the debug function to remove a warning when building
with dynamic debug enabled.
Signed-off-by: Romain Izard
Fixes: 741d2558bf0a ("usb: gadget: udc: atmel: Update endpoint allocation
Add Quectel UC15, UC20, EC21, and EC25. The EC20 is handled by
qcserial due to a USB VID/PID conflict with an existing Acer
device.
Signed-off-by: Dan Williams
---
NOTE: The UC20, EC21, and EC25 should also get a corresponding qmi_wwan
patch but I don't have that lying around
On Thu, Mar 9, 2017 at 11:11 AM, Diego Viola wrote:
> On Wed, Mar 8, 2017 at 5:40 PM, Diego Viola wrote:
>> Hi Greg,
>>
>> On Wed, Mar 8, 2017 at 5:15 PM, Greg KH wrote:
>>> On Wed, Mar 08, 2017 at 03:49:19PM -0300, Diego
On Thu, 2017-03-09 at 10:28 +0100, Oliver Neukum wrote:
> Am Mittwoch, den 08.03.2017, 17:30 -0500 schrieb Balazs Harmath:
> > Hi guys,
> >
> > I’w working with a Quectel EC21 modem and i ran into an issue that
> > the qcserial driver is not getting installed for it.
> > Previously i was working
Hi Alan,
On jeu., mars 09 2017, Alan Stern wrote:
>> @@ -47,6 +47,21 @@
>> #define USB_PHY_IVREF_CTRL 0x440
>> #define USB_PHY_TST_GRP_CTRL0x450
>>
>> +#define USB_SBUSCFG 0x90
>> +#define USB_SBUSCFG_BAWR_SHIFT 0x6
>> +#define
On Thu, 9 Mar 2017, Gregory CLEMENT wrote:
> From: Hua Jing
>
> - Add a new compatible string for the Armada 3700 SoCs
>
> - add sbuscfg support for orion usb controller driver. For the SoCs
> without hlock, need to program BAWR/BARD/AHBBRST fields in the sbuscfg
>
On Wed, Mar 8, 2017 at 5:40 PM, Diego Viola wrote:
> Hi Greg,
>
> On Wed, Mar 8, 2017 at 5:15 PM, Greg KH wrote:
>> On Wed, Mar 08, 2017 at 03:49:19PM -0300, Diego Viola wrote:
>>> It hangs on resume from suspend if I have USB 3.0 enabled on the
With commit "usb: gadget: don't couple configfs to legacy gadgets"
it is possible to build a modular kernel with both built-in configfs
support and modular legacy gadget drivers.
But when building a kernel without modules, it is also necessary to be
able to build with configfs but without any
From: Guenter Roeck
Upstream commit 98d74f9ceaef ("xhci: fix 10 second timeout on removal of
PCI hotpluggable xhci controllers") fixes a problem with hot pluggable PCI
xhci controllers which can result in excessive timeouts, to the point where
the system reports a deadlock.
From: Peter Chen
According to xHCI spec, HCIVERSION containing a BCD encoding
of the xHCI specification revision number, 0100h corresponds
to xHCI version 1.0. Change "100" as "0x100".
Cc: Lu Baolu
Cc: stable
Fixes:
Hi Greg
A few small xhci fixes usb-linus 4.11-rc
-Mathias
Chunfeng Yun (2):
usb: xhci-mtk: check hcc_params after adding primary hcd
usb: xhci: remove dummy extra_priv_size for size of xhci_hcd struct
Guenter Roeck (1):
usb: host: xhci-plat: Fix timeout on removal of hot pluggable xhci
From: Chunfeng Yun
because hcd_priv_size is already size of xhci_hcd struct,
extra_priv_size is not needed anymore for MTK and tegra drivers.
Signed-off-by: Chunfeng Yun
Tested-by: Thierry Reding
Acked-by: Thierry
From: Chunfeng Yun
hcc_params is set in xhci_gen_setup() called from usb_add_hcd(),
so checks the Maximum Primary Stream Array Size in the hcc_params
register after adding primary hcd.
Signed-off-by: Chunfeng Yun
Signed-off-by: Mathias
On 08.03.2017 20:19, Guenter Roeck wrote:
If usb_get_bos_descriptor() returns an error, usb->bos will be NULL.
Nevertheless, it is dereferenced unconditionally in
hub_set_initial_usb2_lpm_policy() if usb2_hw_lpm_capable is set.
This results in a crash.
usb 5-1: unable to get BOS descriptor
...
On Thu, Mar 09, 2017 at 12:04:21PM +0100, Gregory CLEMENT wrote:
> Hi,
>
> The EHCI controller in the Armada 37xx SoCs is the one used on many
> other mvebu SoCs such as the orion5x, the kirkwood, or the
> armada. However, for Armada 37xx an extra initialization step is
> needed: this is the
From febeb10887d5026a489658fd9e911656e76038ac Mon Sep 17 00:00:00 2001
From: Ajay Kaher
Date: Thu, 9 Mar 2017 16:07:54 +0530
Subject: [PATCH v4] USB:Core: BugFix: Proper handling of Race Condition when two
USB class drivers try to call init_usb_class simultaneously
There
On Thu, Mar 09, 2017 at 11:34:25AM +, Ajay Kaher wrote:
> From febeb10887d5026a489658fd9e911656e76038ac Mon Sep 17 00:00:00 2001
> From: Ajay Kaher
> Date: Thu, 9 Mar 2017 16:07:54 +0530
> Subject: [PATCH v4] USB:Core: BugFix: Proper handling of Race Condition when
>
On 9 March 2017 at 18:34, Jun Li wrote:
>
>
>> -Original Message-
>> From: Baolin Wang [mailto:baolin.w...@linaro.org]
>> Sent: Thursday, March 09, 2017 2:11 PM
>> To: Jun Li
>> Cc: NeilBrown ; Felipe Balbi ; Greg KH
>>
The mvebu ARM64 SoCs no longer select PLAT_ORION. However Armada 37xx use
the Orion EHCI controller. This patch allows the Orion EHCI driver to be
built when ARCH_MVEBU is selected.
Signed-off-by: Gregory CLEMENT
---
drivers/usb/host/Kconfig | 2 +-
1 file
From: Hua Jing
- Add a new compatible string for the Armada 3700 SoCs
- add sbuscfg support for orion usb controller driver. For the SoCs
without hlock, need to program BAWR/BARD/AHBBRST fields in the sbuscfg
register to guarantee the AHB master's burst would not
Hi,
The EHCI controller in the Armada 37xx SoCs is the one used on many
other mvebu SoCs such as the orion5x, the kirkwood, or the
armada. However, for Armada 37xx an extra initialization step is
needed: this is the purpose of the first patch.
The second patch allows to build the driver for the
Armada 37xx SoC embedded an EHCI controller. This patch adds the device
tree node enabling its support.
Signed-off-by: Gregory CLEMENT
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 6 ++
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 7 +++
2
> -Original Message-
> From: Baolin Wang [mailto:baolin.w...@linaro.org]
> Sent: Thursday, March 09, 2017 2:11 PM
> To: Jun Li
> Cc: NeilBrown ; Felipe Balbi ; Greg KH
> ; Sebastian Reichel ;
The following changes since commit c1ae3cfa0e89fa1a7ecc4c99031f5e9ae99d9201:
Linux 4.11-rc1 (2017-03-05 12:59:56 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/johan/usb-serial.git
tags/usb-serial-4.11-rc2
for you to fetch changes up to
On Thu, Mar 09, 2017 at 11:08:41AM +0100, Johan Hovold wrote:
> The following changes since commit c1ae3cfa0e89fa1a7ecc4c99031f5e9ae99d9201:
>
> Linux 4.11-rc1 (2017-03-05 12:59:56 -0800)
>
> are available in the git repository at:
>
>
Dear Greg,
Apologies, I sent the patch from my Windows box, using Thunderbird. Entirely
possible
I used the wrong settings. I will do as you suggest.
Regards,
Phil
On 09/03/2017 09:25, Greg KH wrote:
On Wed, Mar 08, 2017 at 10:49:26PM +, Phillip Potter wrote:
Updates the e-mail address
Hello,
Le 09/03/2017 à 08:01, Peter Senna Tschudin a écrit :
> On Wed, Mar 08, 2017 at 02:40:25PM -0800, Jeff Kirsher wrote:
>> On Wed, 2017-03-08 at 17:19 +0100, Romain Perier wrote:
>>> The PCI pool API is deprecated. This commit replaces the PCI pool old
>>> API by the appropriate function
Hello!
On 3/9/2017 11:47 AM, Roger Quadros wrote:
As per [1] issue #4,
"The periodic EP scheduler always tries to schedule the EPs
that have large intervals (interval equal to or greater than
128 microframes) into different microframes. So it maintains
an internal counter and increments for
Am Mittwoch, den 08.03.2017, 17:30 -0500 schrieb Balazs Harmath:
> Hi guys,
>
> I’w working with a Quectel EC21 modem and i ran into an issue that
> the qcserial driver is not getting installed for it.
> Previously i was working with the Quectel EC20 which was working
> properly but the cell
Felipe,
On 08/03/17 16:05, Roger Quadros wrote:
> The streaming_maxburst module parameter is 0 offset (0..15)
> so we must add 1 while using it for wBytesPerInterval
> calculation for the SuperSpeed companion descriptor.
>
> Without this host uvcvideo driver will always see the wrong
>
Am Donnerstag, den 09.03.2017, 06:42 +0100 schrieb Greg KH:
> On Mon, Feb 20, 2017 at 03:38:42PM +0100, Oliver Neukum wrote:
> >
> > There is a small window during which the an URB may
> > remain active after disconnect has returned. If in that case
> > already freed memory may be accessed and
On 03/09/2017 10:26 AM, Reshetova, Elena wrote:
>
>> On 03/09/2017 08:18 AM, Reshetova, Elena wrote:
On Mon, Mar 06, 2017 at 04:21:09PM +0200, Elena Reshetova wrote:
> refcount_t type and corresponding API should be
> used instead of atomic_t when the variable is used as
> a
> On 03/09/2017 08:18 AM, Reshetova, Elena wrote:
> >> On Mon, Mar 06, 2017 at 04:21:09PM +0200, Elena Reshetova wrote:
> >>> refcount_t type and corresponding API should be
> >>> used instead of atomic_t when the variable is used as
> >>> a reference counter. This allows to avoid accidental
>
On 08.03.2017 21:49, Guenter Roeck wrote:
Upstream commit 98d74f9ceaef ("xhci: fix 10 second timeout on removal of
PCI hotpluggable xhci controllers") fixes a problem with hot pluggable PCI
xhci controllers which can result in excessive timeouts, to the point where
the system reports a deadlock.
On Wed, Mar 08, 2017 at 10:49:26PM +, Phillip Potter wrote:
> Updates the e-mail address of Phillip Potter, updater of the Nokia 6288
> entry in drivers/usb/storage/unusual_devs.h
>
> Signed-off-by: Phillip Potter
> ---
> --- a/drivers/usb/storage/unusual_devs.h
On Thu, Mar 09, 2017 at 11:05:57AM +0200, Felipe Balbi wrote:
>
> Hi Greg,
>
> Here's my first set of fixes for this -rc cycle. Let me know if you want
> anything to be changed ;-)
Pulled and pushed out, thanks.
greg k-h
--
To unsubscribe from this list: send the line "unsubscribe linux-usb"
Hi Greg,
Here's my first set of fixes for this -rc cycle. Let me know if you want
anything to be changed ;-)
Cheers
The following changes since commit c1ae3cfa0e89fa1a7ecc4c99031f5e9ae99d9201:
Linux 4.11-rc1 (2017-03-05 12:59:56 -0800)
are available in the git repository at:
Hi Krzysztof,
On Wed, Mar 08, 2017 at 10:00:55AM +0100, Krzysztof Opasiak wrote:
>
> Descriptors says that it's bulk so now question is if it uses
> streams or not. Check your driver or USB traffic.
>
I just grep'ed usb_alloc_streams in the driver, nothing appeared. So it should
be just bulk,
On 03/09/2017 08:18 AM, Reshetova, Elena wrote:
>> On Mon, Mar 06, 2017 at 04:21:09PM +0200, Elena Reshetova wrote:
>>> refcount_t type and corresponding API should be
>>> used instead of atomic_t when the variable is used as
>>> a reference counter. This allows to avoid accidental
>>> refcounter
As per [1] issue #4,
"The periodic EP scheduler always tries to schedule the EPs
that have large intervals (interval equal to or greater than
128 microframes) into different microframes. So it maintains
an internal counter and increments for each large interval
EP added. When the counter is
On Thu, 2017-03-09 at 13:51 +0530, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Monday 06 March 2017 07:19 PM, Chunfeng Yun wrote:
> > the reference clock of HighSpeed port is 48M which comes from PLL;
> > the reference clock of SuperSpeed port is 26M which usually comes
> > from 26M oscillator
Hi,
On Monday 06 March 2017 07:19 PM, Chunfeng Yun wrote:
> the reference clock of HighSpeed port is 48M which comes from PLL;
> the reference clock of SuperSpeed port is 26M which usually comes
> from 26M oscillator directly, but some SoCs are not, add it for
> compatibility, and put them into
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