[PATCH v2 1/2] staging: rtl8723au: core: avoid bitwise arithmetic with forced endianness

source files for new driver - part 1, initially from github according to commit description. On github, this traces back to another bulk commit: 2896bda04353 Add new files in core directory, which is the 1st version of the driver. Signed-off-by: David Decotigny ddeco...@gmail.com --- drivers

[PATCH v2 0/2] staging: rtl8723au: core: endianness issues

to correct recipients, only changed commit descriptions (credits to Dan Carpenter) # Patch Set Summary: David Decotigny (2): staging: rtl8723au: core: avoid bitwise arithmetic with forced endianness staging: rtl8723au: core: remove redundant

[PATCH v2 2/2] staging: rtl8723au: core: remove redundant endianness conversion

/rtl8723au/core/rtw_mlme_ext.c:3911:56:expected unsigned short [unsigned] [usertype] val drivers/staging/rtl8723au/core/rtw_mlme_ext.c:3911:56:got restricted __le16 [usertype] BA_timeout_value Signed-off-by: David Decotigny ddeco...@gmail.com --- drivers/staging/rtl8723au/core