[RFC 2/4] mt76x0: correct RF access via RF_CSR regiser.

[Stanislaw Gruszka]

PCIe version don't use MCU for RF regsisters access. We need
to correct RF CSR method to support up to 127 RF registers.

Signed-off-by: Stanislaw Gruszka <sgrus...@redhat.com>
---
 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c   | 6 ++----
 drivers/net/wireless/mediatek/mt76/mt76x02_regs.h | 4 ++--
 2 files changed, 4 insertions(+), 6 deletions(-)

diff --git a/drivers/net/wireless/mediatek/mt76/mt76x0/phy.c 
b/drivers/net/wireless/mediatek/mt76/mt76x0/phy.c
index ca0a693654a3..33e0ea9707e3 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x0/phy.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x0/phy.c
@@ -37,7 +37,7 @@
        bank = MT_RF_BANK(offset);
        reg = MT_RF_REG(offset);
 
-       if (WARN_ON_ONCE(reg > 64) || WARN_ON_ONCE(bank) > 8)
+       if (WARN_ON_ONCE(reg > 127) || WARN_ON_ONCE(bank) > 8)
                return -EINVAL;
 
        mutex_lock(&dev->reg_atomic_mutex);
@@ -77,7 +77,7 @@
        bank = MT_RF_BANK(offset);
        reg = MT_RF_REG(offset);
 
-       if (WARN_ON_ONCE(reg > 64) || WARN_ON_ONCE(bank) > 8)
+       if (WARN_ON_ONCE(reg > 127) || WARN_ON_ONCE(bank) > 8)
                return -EINVAL;
 
        mutex_lock(&dev->reg_atomic_mutex);
@@ -120,7 +120,6 @@
 
                return mt76_wr_rp(dev, MT_MCU_MEMMAP_RF, &pair, 1);
        } else {
-               WARN_ON_ONCE(1);
                return mt76x0_rf_csr_wr(dev, offset, val);
        }
 }
@@ -139,7 +138,6 @@
                ret = mt76_rd_rp(dev, MT_MCU_MEMMAP_RF, &pair, 1);
                val = pair.value;
        } else {
-               WARN_ON_ONCE(1);
                ret = val = mt76x0_rf_csr_rr(dev, offset);
        }
 
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x02_regs.h 
b/drivers/net/wireless/mediatek/mt76/mt76x02_regs.h
index 24d1e6d747dd..f7de77d09d28 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x02_regs.h
+++ b/drivers/net/wireless/mediatek/mt76/mt76x02_regs.h
@@ -205,8 +205,8 @@
 #define MT_TXQ_STA                     0x0434
 #define        MT_RF_CSR_CFG                   0x0500
 #define MT_RF_CSR_CFG_DATA             GENMASK(7, 0)
-#define MT_RF_CSR_CFG_REG_ID           GENMASK(13, 8)
-#define MT_RF_CSR_CFG_REG_BANK         GENMASK(17, 14)
+#define MT_RF_CSR_CFG_REG_ID           GENMASK(14, 8)
+#define MT_RF_CSR_CFG_REG_BANK         GENMASK(17, 15)
 #define MT_RF_CSR_CFG_WR               BIT(30)
 #define MT_RF_CSR_CFG_KICK             BIT(31)
 
-- 
1.9.3