Hi All,
After further debugging we know the place it hangs.
In function:
static int ath_reset_internal (struct ath_softc *sc, struct ath9k_channel
*hchan)
{
disable_irq(sc->irq);
tasklet_disable(&sc->intr_tq);
tasklet_disable(&sc->bcon_tasklet);
spin_lock_bh(&sc->
> On Sat, Dec 10, 2016 at 02:40:48PM +, Bharat Kumar Gogada wrote:
> > Hi,
> >
> > After taking some more lecroy traces, we see that after 2nd ASSERT from EP
> on ARM64 we see continuous data movement of 32 dwords or 12 dwords and
> never sign of DEASSERT.
> > Comparatively on working traces (x
On Sat, Dec 10, 2016 at 02:40:48PM +, Bharat Kumar Gogada wrote:
> Hi,
>
> After taking some more lecroy traces, we see that after 2nd ASSERT from EP on
> ARM64 we see continuous data movement of 32 dwords or 12 dwords and never
> sign of DEASSERT.
> Comparatively on working traces (x86) aft
Hi,
After taking some more lecroy traces, we see that after 2nd ASSERT from EP on
ARM64 we see continuous data movement of 32 dwords or 12 dwords and never sign
of DEASSERT.
Comparatively on working traces (x86) after 2nd assert there are only BAR
register reads and writes and then DEASSERT, fo
Correcting Manohar Mail ID.
> Hello there,
>
> as this is a thread about ath9k and ARM64, i'm not sure if i should
> answer here or not, but i have similar "stalls" with ath9k on x86_64
> (starting with 4.9rc), stack trace is posted down below where the
> original ARM64 stall traces are.
>
> Gr
Hello there,
as this is a thread about ath9k and ARM64, i'm not sure if i should
answer here or not, but i have similar "stalls" with ath9k on x86_64
(starting with 4.9rc), stack trace is posted down below where the
original ARM64 stall traces are.
Greetings,
Tobias
On 08.12.2016 18:36, K
Sorry, Forgot to add kernel version, we are using 4.6 kernel.
> Hi,
> Can any one tell, when exactly the chip sends ASSERT & DEASSERT in driver.
> It might help us to debug issue further.
>
> Thanks & Regards,
> Bharat
>
> > > > [+cc Kalle, ath9k list]
> >
> > Thanks, but please also CC linux-
Hi,
Can any one tell, when exactly the chip sends ASSERT & DEASSERT in driver.
It might help us to debug issue further.
Thanks & Regards,
Bharat
> > > [+cc Kalle, ath9k list]
>
> Thanks, but please also CC linux-wireless. Full thread below for the folks
> there.
>
> >> On Thu, Dec 08, 2016 a
Bharat Kumar Gogada writes:
> > [+cc Kalle, ath9k list]
Thanks, but please also CC linux-wireless. Full thread below for the
folks there.
>> On Thu, Dec 08, 2016 at 01:49:42PM +, Bharat Kumar Gogada wrote:
>> > Hi,
>> >
>> > Did anyone test Atheros ATH9 driver(drivers/net/wireless/ath/ath9
