From: Chew, Chiau Ee chiau.ee.c...@intel.com
This is to enable PCI mode of Intel BayTrail LPSS I2C.
This commit is created in reference to Wilson's work during
kernel-3.5 development.
Signed-off-by: Chew, Chiau Ee chiau.ee.c...@intel.com
Signed-off-by: Maurice Petallo
From: Chang Rebecca Swee Fun rebecca.swee.fun.ch...@intel.com
Hi all,
Here is a request to create feature branch to host Valley Island PCI
enumerated LPSS I/O device drivers. We expect the patch series to be
removed over time. This will give us time to stage a working code
while we are working
From: Chew, Chiau Ee chiau.ee.c...@intel.com
There is channel resource contention between Intel MID DMA
driver and Designware DMA driver if Intel MID DMA driver is
enabled for LPE Audio usage. Since LPIO devices are tied to
fixed DMA channel numbers, so the Designware DMA controller
has to be
From: Maurice Petallo mauricex.r.peta...@intel.com
Due to power saving purpose, BIOS disabled ulpi phy refclk by default.
Hence, the refclk will only be enabled during device/driver probing.
and disabled during driver removal.
Signed-off-by: Maurice Petallo mauricex.r.peta...@intel.com
From: Chew, Kean Ho kean.ho.c...@intel.com
The clock appears to be unstable when SDCARD host running with
DDR50 mode, thus causing CRC issue. This is to introduce a new
quirk to force host with broken DDR50 mode to run with SDR25
mode.
Signed-off-by: Chew, Kean Ho kean.ho.c...@intel.com
From: Chew, Chiau Ee chiau.ee.c...@intel.com
This will add PCI mode suspend and resume callbacks
to support system suspend to and resume from S3.
Signed-off-by: Chew, Chiau Ee chiau.ee.c...@intel.com
Signed-off-by: Maurice Petallo mauricex.r.peta...@intel.com
---
drivers/dma/dw/pci.c | 36
From: Heikki Krogerus heikki.kroge...@linux.intel.com
Intel BayTrail has two HS-UARTs with 64 byte fifo, support
for DMA and support for 16750 compatible Auto Flow Control.
Signed-off-by: Heikki Krogerus heikki.kroge...@linux.intel.com
Signed-off-by: Greg Kroah-Hartman gre...@linuxfoundation.org
From: H Hartley Sweeten hartl...@visionengravers.com
Add a simple sysfs interface to the generic PWM framework.
/sys/class/pwm/
`-- pwmchipN/ for each PWM chip
|-- export (w/o) ask the kernel to export a PWM channel
|-- npwm(r/o) number of PWM
From: Chew, Chiau Ee chiau.ee.c...@intel.com
Provide option to set the HCNT, LCNT and SDA if the target values are known
ahead. Instead of depends on formula to calculate the HCNT and LCNT.
Signed-off-by: Chew, Chiau Ee chiau.ee.c...@intel.com
Signed-off-by: Maurice Petallo
From: Maurice Petallo mauricex.r.peta...@intel.com
sdhc host may share same interrupt line with other IO devices that
trigger interrupt frequently, like USB. In this case, we encountered
continous prints of warning message got irq while runtime suspended
when the interrupt triggered by other IO
From: Chew, Kean Ho kean.ho.c...@intel.com
In to_irq() callback, we create the hwirq to linux irq
mapping for the requested GPIO pin. Hence, we unamp
the mapping when the gpio pin is being released.
Signed-off-by: Chew, Kean Ho kean.ho.c...@intel.com
Signed-off-by: Chew, Chiau Ee
From: Chew, Chiau Ee chiau.ee.c...@intel.com
Declare host controller supports 10-bit addressing mode
functionality.
Signed-off-by: Chew, Chiau Ee chiau.ee.c...@intel.com
Signed-off-by: Maurice Petallo mauricex.r.peta...@intel.com
---
drivers/i2c/busses/i2c-designware-pcidrv.c |1 +
1 file
From: Chew, Chiau Ee chiau.ee.c...@intel.com
This commit enables the following:
- setup clock tree for PCI mode SPI, DMA and PWM host
as the controller drivers require clock information during
device/driver probe
- register SPI slave
Signed-off-by: Chew, Chiau Ee chiau.ee.c...@intel.com
From: Alan Stern st...@rowland.harvard.edu
When CONFIG_HAS_DMA isn't enabled, the UDC core gets build errors:
drivers/built-in.o: In function `dma_set_coherent_mask':
include/linux/dma-mapping.h:93: undefined reference to `dma_supported'
include/linux/dma-mapping.h:93: undefined reference to
From: Chew, Chiau Ee chiau.ee.c...@intel.com
This is to fix the card detection failure when the
card detect status is read from the GPIO status register.
Signed-off-by: Chew, Chiau Ee chiau.ee.c...@intel.com
Signed-off-by: Maurice Petallo mauricex.r.peta...@intel.com
---
From: Chang, Rebecca Swee Fun rebecca.swee.fun.ch...@intel.com
Add PCI ID of BYT SMBUS.
Signed-off-by: Chew, Kean Ho kean.ho.c...@intel.com
Signed-off-by: Maurice Petallo mauricex.r.peta...@intel.com
Signed-off-by: Chang, Rebecca Swee Fun rebecca.swee.fun.ch...@intel.com
---
From: Chew, Chiau Ee chiau.ee.c...@intel.com
This will enable high speed baud rates namely 1M, 2M, 3M, and 4M
in Intel Baytrail Designware controller.
Signed-off-by: Chew, Chiau Ee chiau.ee.c...@intel.com
Signed-off-by: Maurice Petallo mauricex.r.peta...@intel.com
---
From: Chew, Chiau Ee chiau.ee.c...@intel.com
The pxa2xx pci glue layer only support CE4100 SPI port
by default. To add BYT SPI port support, we make it a
generic PCI glue layer by renaming ce4100_xxx to
pxa2xx_spi_xxx.
This commit is created in reference to Mika's commit
during kernel-3.5
From: Chew, Chiau Ee chiau.ee.c...@intel.com
Allow CONFIG_X86_INTEL_LPSS to be set when ACPI
or PCI is set.
Signed-off-by: Chew, Chiau Ee chiau.ee.c...@intel.com
Signed-off-by: Maurice Petallo mauricex.r.peta...@intel.com
---
arch/x86/Kconfig |2 +-
1 file changed, 1 insertion(+), 1
From: Chew, Chiau Ee chiau.ee.c...@intel.com
This is to add support for BYT PCI mode PWM.
Signed-off-by: Chew, Chiau Ee chiau.ee.c...@intel.com
Signed-off-by: Chang, Rebecca Swee Fun rebecca.swee.fun.ch...@intel.com
Signed-off-by: Maurice Petallo mauricex.r.peta...@intel.com
---
From: Maurice Petallo mauricex.r.peta...@intel.com
Use BYT DMA PCI domain:bus:slot.func identification
as device name input during clkdev registration.
Signed-off-by: Maurice Petallo mauricex.r.peta...@intel.com
---
arch/x86/platform/byt/byt-board.c |2 +-
1 file changed, 1 insertion(+), 1
From: Chew, Kean Ho kean.ho.c...@intel.com
BayTrail GPIO NORTH, SOUTH and SUS clusters use IRQ48,
49 and 50 respectively. On non-ACPI system, we need
to setup IOAPIC RTE for device that use interrupt
beyond IRQ23.
Signed-off-by: Chew, Kean Ho kean.ho.c...@intel.com
Signed-off-by: Chew, Chiau Ee
From: Chew, Kean Ho kean.ho.c...@intel.com
This is to cater the need for non-ACPI system whereby
a platform device has to be created in order to bind
with the BYT Pinctrl GPIO platform driver.
Signed-off-by: Chew, Kean Ho kean.ho.c...@intel.com
Signed-off-by: Chew, Chiau Ee
From: Chew, Chiau Ee chiau.ee.c...@intel.com
This to improve the accuracy of base_unit calculation
so that the resulting PWM frquency will be more
optimal.
Signed-off-by: Chew, Kean Ho kean.ho.c...@intel.com
Signed-off-by: Chew, Chiau Ee chiau.ee.c...@intel.com
Signed-off-by: Maurice Petallo
From: Mika Westerberg mika.westerb...@linux.intel.com
Add support for Intel Low Power I/O subsystem PWM controllers found on some
newer intel chipsets.
Signed-off-by: Mika Westerberg mika.westerb...@linux.intel.com
This patch is pulled from Mika's git tree previousy. The git
tree is no longer
From: Felipe Balbi ba...@ti.com
usb_gadget_set_state() will call sysfs_notify()
which might sleep. Some users might want to call
usb_gadget_set_state() from the very IRQ handler
which actually changes the gadget state.
Instead of having every UDC driver add their own
workqueue for such a simple
I am using Dora version of Yocto with my BSP.
There is a compilation issue and the cause is certain values
(V4L2_MBUS_FMT_ARGB_1X32 and V4L2_MBUS_FMT_AYUV8_1X32) not defined in the
following file
build/tmp/sysroots/machine/usr/include/linux/v4l2-mediabus.h
which is needed by media-ctl's
On 14-04-07 08:10 AM, Sathish Kumar Balasubramaniam -ERS, HCL Tech wrote:
I am using Dora version of Yocto with my BSP.
There is a compilation issue and the cause is certain values
(V4L2_MBUS_FMT_ARGB_1X32 and V4L2_MBUS_FMT_AYUV8_1X32) not defined
in the following file
On 14-04-07 11:17 AM, rebecca.swee.fun.ch...@intel.com wrote:
From: Chang Rebecca Swee Fun rebecca.swee.fun.ch...@intel.com
Hi all,
Adding Darren (just in case he missed this).
Here is a request to create feature branch to host Valley Island PCI
enumerated LPSS I/O device drivers. We
-Original Message-
From: Bruce Ashfield [mailto:bruce.ashfi...@windriver.com]
Sent: 08 April, 2014 3:04 AM
To: Chang, Rebecca Swee Fun; linux-yocto@yoctoproject.org; Darren Hart
Subject: Re: [linux-yocto] [PATCH 00/29] Create new feature branch for
Valley Island BSP
On 14-04-07
On 2014-04-07, 8:28 PM, Chang, Rebecca Swee Fun wrote:
-Original Message-
From: Bruce Ashfield [mailto:bruce.ashfi...@windriver.com]
Sent: 08 April, 2014 3:04 AM
To: Chang, Rebecca Swee Fun; linux-yocto@yoctoproject.org; Darren Hart
Subject: Re: [linux-yocto] [PATCH 00/29] Create new
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