From: Heikki Krogerus heikki.kroge...@linux.intel.com
DMA engines usually expect the fifo trigger level to be
aligned with the burst size. It should not be changed even
with small baud rates. This will fix an issue with
Designware DMA engine where the data can not be transferred
over UART with
From: H Hartley Sweeten hartl...@visionengravers.com
Add a simple sysfs interface to the generic PWM framework.
/sys/class/pwm/
`-- pwmchipN/ for each PWM chip
|-- export (w/o) ask the kernel to export a PWM channel
|-- npwm(r/o) number of PWM
From: Chew, Kean Ho kean.ho.c...@intel.com
The requested gpio pin must has the func_pin_mux field set
to GPIO function by BIOS/FW in advanced. Else, the gpio pin
request would fail. This is to ensure that we do not expose
any gpio pins which shall be used for alternate functions,
for eg: wakeup
From: Mika Westerberg mika.westerb...@linux.intel.com
Intel Baytrail I2C controllers can be enumerated from PCI as well as from
ACPI. In order to support this add the Baytrail PCI IDs to the driver.
Signed-off-by: Mika Westerberg mika.westerb...@linux.intel.com
Signed-off-by: Wolfram Sang
From: Adrian Hunter adrian.hun...@intel.com
If the SDHCI irq is shared with another device then the interrupt
handler can get called while SDHCI is runtime suspended. That is
harmless but the warning message is not useful so remove it. Also
returning IRQ_NONE is more appropriate.
From: Chew, Chiau Ee chiau.ee.c...@intel.com
Intel BayTrail LPSS consists of two PWM controllers which can
be enumerated from ACPI namespace. This change will cause
platform device objects to be created for Intel BayTrail PWM
controllers which will allow the pwm-lpss driver to bind to them
and
From: Chew, Chiau Ee chiau.ee.c...@intel.com
The pxa2xx pci glue layer only support CE4100 SPI port
by default. To add BYT SPI port support, we make it a
generic PCI glue layer by renaming ce4100_xxx to
pxa2xx_spi_xxx.
This commit is created in reference to Mika's commit
during kernel-3.5
From: Chew, Chiau Ee chiau.ee.c...@intel.com
On Intel BayTrail, there was case whereby the resulting fast mode
bus speed becomes slower (~20% slower compared to expected speed)
if using the HCNT/LCNT calculated in the core layer. Thus, this
patch is added to allow pci glue layer to pass in
From: Alan Stern st...@rowland.harvard.edu
When CONFIG_HAS_DMA isn't enabled, the UDC core gets build errors:
drivers/built-in.o: In function `dma_set_coherent_mask':
include/linux/dma-mapping.h:93: undefined reference to `dma_supported'
include/linux/dma-mapping.h:93: undefined reference to
From: Chew, Chiau Ee chiau.ee.c...@intel.com
BYT ACPI mode SPI not read/writing correctly at low speeds
using DMA mode. Fix the issue by changing DMA SRC_MSIZE and
DEST_MSIZE of SPI FIFO side from 16 to 32.
Signed-off-by: Chew, Chiau Ee chiau.ee.c...@intel.com
Signed-off-by: Maurice Petallo
From: Chew, Chiau Ee chiau.ee.c...@intel.com
All the I2C controllers on Intel BayTrail LPSS subsystem able
to support 10-bit addressing mode functionality.
Signed-off-by: Chew, Chiau Ee chiau.ee.c...@intel.com
Signed-off-by: Ong, Boon Leong boon.leong@intel.com
Signed-off-by: Wolfram Sang
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