From: Srinivas Pandruvada
commit 745698c37c08f48fb5ad3c0cb7ee955bd5701d4a upstream.
Read SLP_S0 address from ACPI LPIT table when present and use PMC
specific SLP_S0 offset to get the base address of PMC MMIO.
Signed-off-by: Rajneesh Bhardwaj
From: Rajneesh Bhardwaj
commit 291101f6a73566f5d1ab597784288c5bc85906fd upstream.
This adds support for Cannonlake PCH which is used by Cannonlake and
Coffeelake SoCs.
Signed-off-by: Srinivas Pandruvada
Signed-off-by: Rajneesh
From: Srinivas Pandruvada
commit eeb2d80d502af28e5660ff4bbe00f90ceb82c2db upstream.
Add functionality to read LPIT table, which provides:
- Sysfs interface to read residency counters via
/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us
From: Srinivas Pandruvada
commit 9383bbadfe29fe8319e2245b75a508db9abd7b87 upstream.
Export lpit_read_residency_count_address(), so that it can be used from
drivers built as module. With the recent changes, the builtin_pci
functionality of the intel_pmc_core
From: Rajneesh Bhardwaj
commit 661405bd817b209ac9bd4812c63d90873a7f2993 upstream.
Intel CoffeeLake SoC uses CPU ID of KabyLake but has Cannonlake PCH, so in
this case PMC register details from Cannonlake PCH must be used.
In order to identify whether the given
From: Rajneesh Bhardwaj
commit 941691ef2197944a202d7870dcd7da3fb0391c65 upstream.
Recently sent patch 'platform/x86: intel_pmc_core: Remove unused EXPORTED
API' missed to remove the header file 'arch/x86/include/asm/pmc_core.h'
which was solely used to declare the
From: Rajneesh Bhardwaj
commit 00f8b2fce4da2296bafc1de6a46510a13ef60938 upstream.
Use ICPU macro to refactor code related to x86_cpu_id for better
readability.
Suggested-by: Andy Shevchenko
Signed-off-by: Srinivas Pandruvada
From: Rajneesh Bhardwaj
commit 750e0f570b7145870d40f07337f3356c18e0abd4 upstream.
When on a platform if we can't show MPHY and PLL status, don't even bother
to create a debugfs entry as it will fail anyway. In fact unless OEM builds
a special BIOS for test, it will
From: Srinivas Pandruvada
commit 21ae43570940f8393a80369f62a3880bd64daad8 upstream.
The Only use of PCI device enumeration here is to get the PMC base address
which is a fixed value i.e. 0xFE00. On some platforms this can be read
through a non standard
From: Rajneesh Bhardwaj
commit 12d614a0dcaee9668c641fcaa9f524da861a765e upstream.
Though ChromeOs uses the exported API as part of their S0ix failsafe
mechanism, there is no active consumer of this API in upstream kernel.
We can revisit this when ChromeOs kernel
From: Rajneesh Bhardwaj
commit 8c9180dd2c2a5f1356121cd87b373d9881b41c65 upstream.
base_address field is redundant and unused in the driver so get rid of it.
Signed-off-by: Srinivas Pandruvada
Signed-off-by: Rajneesh Bhardwaj
Add PMC Driver support for Intel Core SoC.
Signed-off-by: Liwei Song
---
features/intel-pmc/intel-pmc-core.cfg | 1 +
features/intel-pmc/intel-pmc-core.scc | 4
2 files changed, 5 insertions(+)
create mode 100644 features/intel-pmc/intel-pmc-core.cfg
create mode
From: Song Hongyan
commit 1e3b74a2f844c3fcd8b3206178b8c6524aa34d05 upstream.
Added PCI ID for Cannon Lake ISH.
Signed-off-by: Song Hongyan
Acked-by: Srinivas Pandruvada
Signed-off-by: Jiri Kosina
From: Srinivas Pandruvada
commit c977b98bbef5898ed3d30b08ea67622e9e82082a upstream.
Although this driver did pretty good job in abstracting PCH specific
interfaces, but still there are some loose ends. For example
SLP_S0 counter (for reading SLP_S0
From: Srinivas Pandruvada
commit 7103f6b23392c0a57ceba7915f72fa7bf11d2a90 upstream.
Added PCI ID for Cannon Lake and Coffee Lake laptop/desktop skews.
Signed-off-by: Srinivas Pandruvada
Signed-off-by: Jiri Kosina
Hi Bruce,
These series patches use to add Intel PMC core and Intel ISH support
on CoffeeLake board. All patches backported from upstream.
It also include one kernel-cache patch which used to enable
CONFIG_INTEL_PMC_CORE for intel-pmc-core driver.
Thanks,
Liwei.
Liwei Song (1):
From: Song Hongyan
commit 1694130910cd654a9215fbc0244975e3cf208fc1 upstream.
Added PCI ID for Gemini Lake ISH.
Signed-off-by: Song Hongyan
Acked-by: Srinivas Pandruvada
Signed-off-by: Jiri Kosina
From: Limeng
Hi Bruce,
Please help to meger below patch into linux-yocto, kernel 4.12, branch is
standard/base
0001-driver-clk-socfpga-remove-unused-variable.patch
clk-pll-s10.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
thanks,
Limeng
--
From: Limeng
commit f826ccc79752(“FogBugz #488843-2: add clock driver
for Stratix10 SOC”) introduce reg2, but it is not used.
So, remove it.
Signed-off-by: Meng Li
---
drivers/clk/socfpga/clk-pll-s10.c | 2 +-
1 file changed, 1 insertion(+), 1
On 03/22/2018 12:00 PM, Bruce Ashfield wrote:
On 03/22/2018 04:49 AM, Nathan Rossi wrote:
On 22 March 2018 at 15:33, Bruce Ashfield
wrote:
On 03/20/2018 10:10 AM, Nathan Rossi wrote:
This change adds WiFi driver configuration fragments. The fragments are
split
On 03/22/2018 04:49 AM, Nathan Rossi wrote:
On 22 March 2018 at 15:33, Bruce Ashfield wrote:
On 03/20/2018 10:10 AM, Nathan Rossi wrote:
This change adds WiFi driver configuration fragments. The fragments are
split into vendor and interface files to allow for
On 22 March 2018 at 15:33, Bruce Ashfield wrote:
> On 03/20/2018 10:10 AM, Nathan Rossi wrote:
>>
>> This change adds WiFi driver configuration fragments. The fragments are
>> split into vendor and interface files to allow for easy selection of
>> drivers for
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