From: "Chai, Chong Yi" <chong.yi.c...@intel.com>
---
features/soc/baytrail/baytrail.scc | 10 +
...Intel-MID-DMA-driver-and-Designware-DMA-d.patch | 39 ++
...dw-allocate-memory-in-two-stages-in-probe.patch | 88 +++++
...w-apply-both-HS-interfaces-and-remove-sla.patch | 155 ++++++++
...w-convert-dw_dma_slave-to-use-explicit-HS.patch | 114 ++++++
.../dmaengine-dw-enable-clock-before-access.patch | 48 +++
.../dmaengine-dw-fix-checkpatch.pl-warnings.patch | 40 ++
...ne-dw-fix-regression-in-dw_probe-function.patch | 114 ++++++
...gine-dw-introduce-generic-filter-function.patch | 195 ++++++++++
...ne-dw-move-clock-operations-to-platform.c.patch | 203 ++++++++++
...-dw-move-dw_dmac.h-to-where-it-belongs-to.patch | 412 +++++++++++++++++++++
11 files changed, 1418 insertions(+)
create mode 100644
features/soc/baytrail/dma-dw-Fix-Intel-MID-DMA-driver-and-Designware-DMA-d.patch
create mode 100644
features/soc/baytrail/dma-dw-allocate-memory-in-two-stages-in-probe.patch
create mode 100644
features/soc/baytrail/dmaengine-dw-apply-both-HS-interfaces-and-remove-sla.patch
create mode 100644
features/soc/baytrail/dmaengine-dw-convert-dw_dma_slave-to-use-explicit-HS.patch
create mode 100644
features/soc/baytrail/dmaengine-dw-enable-clock-before-access.patch
create mode 100644
features/soc/baytrail/dmaengine-dw-fix-checkpatch.pl-warnings.patch
create mode 100644
features/soc/baytrail/dmaengine-dw-fix-regression-in-dw_probe-function.patch
create mode 100644
features/soc/baytrail/dmaengine-dw-introduce-generic-filter-function.patch
create mode 100644
features/soc/baytrail/dmaengine-dw-move-clock-operations-to-platform.c.patch
create mode 100644
features/soc/baytrail/dmaengine-dw-move-dw_dmac.h-to-where-it-belongs-to.patch
diff --git a/features/soc/baytrail/baytrail.scc
b/features/soc/baytrail/baytrail.scc
index bd2bb4b..03a22d0 100644
--- a/features/soc/baytrail/baytrail.scc
+++ b/features/soc/baytrail/baytrail.scc
@@ -44,3 +44,13 @@ patch mmc-block-refactor-read-only-handling.patch
patch mmc-block-implement-write-request-blocking.patch
patch mmc-support-whole-device-temporary-write-protection-.patch
patch mmc-block-Fix-checkpatch.pl-warning.patch
+patch dma-dw-Fix-Intel-MID-DMA-driver-and-Designware-DMA-d.patch
+patch dma-dw-allocate-memory-in-two-stages-in-probe.patch
+patch dmaengine-dw-enable-clock-before-access.patch
+patch dmaengine-dw-fix-regression-in-dw_probe-function.patch
+patch dmaengine-dw-move-dw_dmac.h-to-where-it-belongs-to.patch
+patch dmaengine-dw-convert-dw_dma_slave-to-use-explicit-HS.patch
+patch dmaengine-dw-apply-both-HS-interfaces-and-remove-sla.patch
+patch dmaengine-dw-introduce-generic-filter-function.patch
+patch dmaengine-dw-move-clock-operations-to-platform.c.patch
+patch dmaengine-dw-fix-checkpatch.pl-warnings.patch
diff --git
a/features/soc/baytrail/dma-dw-Fix-Intel-MID-DMA-driver-and-Designware-DMA-d.patch
b/features/soc/baytrail/dma-dw-Fix-Intel-MID-DMA-driver-and-Designware-DMA-d.patch
new file mode 100644
index 0000000..4fd2897
--- /dev/null
+++
b/features/soc/baytrail/dma-dw-Fix-Intel-MID-DMA-driver-and-Designware-DMA-d.patch
@@ -0,0 +1,39 @@
+From 3e0266d1190c6727f7757c069563aedb9a559fc5 Mon Sep 17 00:00:00 2001
+From: "Chew, Chiau Ee" <chiau.ee.c...@intel.com>
+Date: Wed, 8 May 2013 16:03:20 +0800
+Subject: [PATCH 003/164] dma: dw: Fix Intel MID DMA driver and Designware DMA
+ driver loading sequence
+
+There is channel resource contention between Intel MID DMA
+driver and Designware DMA driver if Intel MID DMA driver is
+enabled for LPE Audio usage. Since LPIO devices are tied to
+fixed DMA channel numbers, so the Designware DMA controller
+has to be first enumerated in order to occupy the required
+channel number.
+
+Signed-off-by: Chew, Chiau Ee <chiau.ee.c...@intel.com>
+Signed-off-by: Maurice Petallo <mauricex.r.peta...@intel.com>
+---
+ drivers/dma/Makefile | 2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
+index a029d0f4..3df1ac8 100644
+--- a/drivers/dma/Makefile
++++ b/drivers/dma/Makefile
+@@ -7,7 +7,6 @@ obj-$(CONFIG_DMA_ACPI) += acpi-dma.o
+ obj-$(CONFIG_DMA_OF) += of-dma.o
+
+ obj-$(CONFIG_NET_DMA) += iovlock.o
+-obj-$(CONFIG_INTEL_MID_DMAC) += intel_mid_dma.o
+ obj-$(CONFIG_DMATEST) += dmatest.o
+ obj-$(CONFIG_INTEL_IOATDMA) += ioat/
+ obj-$(CONFIG_INTEL_IOP_ADMA) += iop-adma.o
+@@ -44,3 +43,4 @@ obj-$(CONFIG_DMA_JZ4740) += dma-jz4740.o
+ obj-$(CONFIG_TI_CPPI41) += cppi41.o
+ obj-$(CONFIG_K3_DMA) += k3dma.o
+ obj-$(CONFIG_MOXART_DMA) += moxart-dma.o
++obj-$(CONFIG_INTEL_MID_DMAC) += intel_mid_dma.o
+--
+1.7.7.6
+
diff --git
a/features/soc/baytrail/dma-dw-allocate-memory-in-two-stages-in-probe.patch
b/features/soc/baytrail/dma-dw-allocate-memory-in-two-stages-in-probe.patch
new file mode 100644
index 0000000..e0bdb61
--- /dev/null
+++ b/features/soc/baytrail/dma-dw-allocate-memory-in-two-stages-in-probe.patch
@@ -0,0 +1,88 @@
+From eabd6e958af4415d69eee87aad547185c14ae624 Mon Sep 17 00:00:00 2001
+From: Andy Shevchenko <andriy.shevche...@linux.intel.com>
+Date: Wed, 5 Mar 2014 15:48:12 +0200
+Subject: [PATCH 032/164] dma: dw: allocate memory in two stages in probe
+
+This makes the probe() function a little bit clearer.
+
+Signed-off-by: Andy Shevchenko <andriy.shevche...@linux.intel.com>
+Signed-off-by: Vinod Koul <vinod.k...@intel.com>
+(cherry picked from commit 000871ce0336572f5b126a4d7f1ec13fc9adfda2)
+Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.moha...@intel.com>
+---
+ drivers/dma/dw/core.c | 17 ++++++++++-------
+ drivers/dma/dw/regs.h | 4 ++--
+ 2 files changed, 12 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
+index b0972b3..c4fbd3e 100644
+--- a/drivers/dma/dw/core.c
++++ b/drivers/dma/dw/core.c
+@@ -1477,7 +1477,6 @@ static void dw_dma_off(struct dw_dma *dw)
+ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
+ {
+ struct dw_dma *dw;
+- size_t size;
+ bool autocfg;
+ unsigned int dw_params;
+ unsigned int nr_channels;
+@@ -1485,6 +1484,13 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct
dw_dma_platform_data *pdata)
+ int err;
+ int i;
+
++ dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL);
++ if (!dw)
++ return -ENOMEM;
++
++ dw->regs = chip->regs;
++ chip->dw = dw;
++
+ dw_params = dma_read_byaddr(chip->regs, DW_PARAMS);
+ autocfg = dw_params >> DW_PARAMS_EN & 0x1;
+
+@@ -1507,9 +1513,9 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct
dw_dma_platform_data *pdata)
+ else
+ nr_channels = pdata->nr_channels;
+
+- size = sizeof(struct dw_dma) + nr_channels * sizeof(struct dw_dma_chan);
+- dw = devm_kzalloc(chip->dev, size, GFP_KERNEL);
+- if (!dw)
++ dw->chan = devm_kcalloc(chip->dev, nr_channels, sizeof(*dw->chan),
++ GFP_KERNEL);
++ if (!dw->chan)
+ return -ENOMEM;
+
+ dw->clk = devm_clk_get(chip->dev, "hclk");
+@@ -1517,9 +1523,6 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct
dw_dma_platform_data *pdata)
+ return PTR_ERR(dw->clk);
+ clk_prepare_enable(dw->clk);
+
+- dw->regs = chip->regs;
+- chip->dw = dw;
+-
+ /* Get hardware configuration parameters */
+ if (autocfg) {
+ max_blk_size = dma_readl(dw, MAX_BLK_SIZE);
+diff --git a/drivers/dma/dw/regs.h b/drivers/dma/dw/regs.h
+index deb4274..bb98d3e 100644
+--- a/drivers/dma/dw/regs.h
++++ b/drivers/dma/dw/regs.h
+@@ -252,13 +252,13 @@ struct dw_dma {
+ struct tasklet_struct tasklet;
+ struct clk *clk;
+
++ /* channels */
++ struct dw_dma_chan *chan;
+ u8 all_chan_mask;
+
+ /* hardware configuration */
+ unsigned char nr_masters;
+ unsigned char data_width[4];
+-
+- struct dw_dma_chan chan[0];
+ };
+
+ static inline struct dw_dma_regs __iomem *__dw_regs(struct dw_dma *dw)
+--
+1.7.7.6
+
diff --git
a/features/soc/baytrail/dmaengine-dw-apply-both-HS-interfaces-and-remove-sla.patch
b/features/soc/baytrail/dmaengine-dw-apply-both-HS-interfaces-and-remove-sla.patch
new file mode 100644
index 0000000..a0144f3
--- /dev/null
+++
b/features/soc/baytrail/dmaengine-dw-apply-both-HS-interfaces-and-remove-sla.patch
@@ -0,0 +1,155 @@
+From d2b2300659467eade49d809c7c3f85ff31eddbe9 Mon Sep 17 00:00:00 2001
+From: Andy Shevchenko <andriy.shevche...@linux.intel.com>
+Date: Tue, 19 Aug 2014 20:29:15 +0300
+Subject: [PATCH 037/164] dmaengine: dw: apply both HS interfaces and remove
+ slave_id usage
+
+Instead of one request line member let's use both source and destination ones.
+Usually we have no such hardware except Atmel MMC controller found on AVR32
+platform (see arch/avr32/mach-at32ap/at32ap700x.c and
+drivers/mmc/host/atmel-mci.c).
+
+This patch removes slave_id usage since it'll be removed from the generic
+structure in later. This breaks the non-ACPI / non-DT cases for the users of
+the driver, i.e. SPI and HSUART. However, these cases mean only PCI enumerated
+devices for now, which is anyway broken (considering more than one DMA
+controller in the system) and this patch series is intended to fix that
+eventually.
+
+The ACPI and DT cases shall be aware of the channel direction when setting
+request lines, but this is a minor problem that would be addressed in future.
+
+Suggested-by: Arnd Bergmann <a...@arndb.de>
+Signed-off-by: Andy Shevchenko <andriy.shevche...@linux.intel.com>
+Signed-off-by: Vinod Koul <vinod.k...@intel.com>
+(cherry picked from commit 8950052029874a6738552debb45077c596e90e6b)
+Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.moha...@intel.com>
+---
+ drivers/dma/dw/core.c | 32 ++------------------------------
+ drivers/dma/dw/platform.c | 6 ++++--
+ drivers/dma/dw/regs.h | 7 ++++---
+ 3 files changed, 10 insertions(+), 35 deletions(-)
+
+diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
+index 25abadd..9a1eb07 100644
+--- a/drivers/dma/dw/core.c
++++ b/drivers/dma/dw/core.c
+@@ -37,24 +37,6 @@
+ * which does not support descriptor writeback.
+ */
+
+-static inline bool is_request_line_unset(struct dw_dma_chan *dwc)
+-{
+- return dwc->request_line == (typeof(dwc->request_line))~0;
+-}
+-
+-static inline void dwc_set_masters(struct dw_dma_chan *dwc)
+-{
+- struct dw_dma *dw = to_dw_dma(dwc->chan.device);
+- struct dw_dma_slave *dws = dwc->chan.private;
+- unsigned char mmax = dw->nr_masters - 1;
+-
+- if (!is_request_line_unset(dwc))
+- return;
+-
+- dwc->src_master = min_t(unsigned char, mmax, dwc_get_sms(dws));
+- dwc->dst_master = min_t(unsigned char, mmax, dwc_get_dms(dws));
+-}
+-
+ #define DWC_DEFAULT_CTLLO(_chan) ({ \
+ struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \
+ struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \
+@@ -158,10 +140,8 @@ static void dwc_initialize(struct dw_dma_chan *dwc)
+ cfghi |= DWC_CFGH_DST_PER(dws->dst_id);
+ cfghi |= DWC_CFGH_SRC_PER(dws->src_id);
+ } else {
+- if (dwc->direction == DMA_MEM_TO_DEV)
+- cfghi = DWC_CFGH_DST_PER(dwc->request_line);
+- else if (dwc->direction == DMA_DEV_TO_MEM)
+- cfghi = DWC_CFGH_SRC_PER(dwc->request_line);
++ cfghi |= DWC_CFGH_DST_PER(dwc->dst_id);
++ cfghi |= DWC_CFGH_SRC_PER(dwc->src_id);
+ }
+
+ channel_writel(dwc, CFG_LO, cfglo);
+@@ -963,10 +943,6 @@ set_runtime_config(struct dma_chan *chan, struct
dma_slave_config *sconfig)
+ memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig));
+ dwc->direction = sconfig->direction;
+
+- /* Take the request line from slave_id member */
+- if (is_request_line_unset(dwc))
+- dwc->request_line = sconfig->slave_id;
+-
+ convert_burst(&dwc->dma_sconfig.src_maxburst);
+ convert_burst(&dwc->dma_sconfig.dst_maxburst);
+
+@@ -1119,8 +1095,6 @@ static int dwc_alloc_chan_resources(struct dma_chan
*chan)
+ * doesn't mean what you think it means), and status writeback.
+ */
+
+- dwc_set_masters(dwc);
+-
+ spin_lock_irqsave(&dwc->lock, flags);
+ i = dwc->descs_allocated;
+ while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) {
+@@ -1178,7 +1152,6 @@ static void dwc_free_chan_resources(struct dma_chan
*chan)
+ list_splice_init(&dwc->free_list, &list);
+ dwc->descs_allocated = 0;
+ dwc->initialized = false;
+- dwc->request_line = ~0;
+
+ /* Disable interrupts */
+ channel_clear_bit(dw, MASK.XFER, dwc->mask);
+@@ -1600,7 +1573,6 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct
dw_dma_platform_data *pdata)
+ channel_clear_bit(dw, CH_EN, dwc->mask);
+
+ dwc->direction = DMA_TRANS_NONE;
+- dwc->request_line = ~0;
+
+ /* Hardware configuration */
+ if (autocfg) {
+diff --git a/drivers/dma/dw/platform.c b/drivers/dma/dw/platform.c
+index fe8b0c9..d878d22 100644
+--- a/drivers/dma/dw/platform.c
++++ b/drivers/dma/dw/platform.c
+@@ -41,7 +41,8 @@ static bool dw_dma_of_filter(struct dma_chan *chan, void
*param)
+ if (chan->device != &fargs->dw->dma)
+ return false;
+
+- dwc->request_line = fargs->req;
++ dwc->src_id = fargs->req;
++ dwc->dst_id = fargs->req;
+ dwc->src_master = fargs->src;
+ dwc->dst_master = fargs->dst;
+
+@@ -88,7 +89,8 @@ static bool dw_dma_acpi_filter(struct dma_chan *chan, void
*param)
+ chan->chan_id != dma_spec->chan_id)
+ return false;
+
+- dwc->request_line = dma_spec->slave_id;
++ dwc->src_id = dma_spec->slave_id;
++ dwc->dst_id = dma_spec->slave_id;
+ dwc->src_master = dwc_get_sms(NULL);
+ dwc->dst_master = dwc_get_dms(NULL);
+
+diff --git a/drivers/dma/dw/regs.h b/drivers/dma/dw/regs.h
+index af02439..0e82d99 100644
+--- a/drivers/dma/dw/regs.h
++++ b/drivers/dma/dw/regs.h
+@@ -221,9 +221,10 @@ struct dw_dma_chan {
+ bool nollp;
+
+ /* custom slave configuration */
+- unsigned int request_line;
+- unsigned char src_master;
+- unsigned char dst_master;
++ u8 src_id;
++ u8 dst_id;
++ u8 src_master;
++ u8 dst_master;
+
+ /* configuration passed via DMA_SLAVE_CONFIG */
+ struct dma_slave_config dma_sconfig;
+--
+1.7.7.6
+
diff --git
a/features/soc/baytrail/dmaengine-dw-convert-dw_dma_slave-to-use-explicit-HS.patch
b/features/soc/baytrail/dmaengine-dw-convert-dw_dma_slave-to-use-explicit-HS.patch
new file mode 100644
index 0000000..913556a
--- /dev/null
+++
b/features/soc/baytrail/dmaengine-dw-convert-dw_dma_slave-to-use-explicit-HS.patch
@@ -0,0 +1,114 @@
+From 3a4c583b4b77ffdca96e950750019de6b719104a Mon Sep 17 00:00:00 2001
+From: Andy Shevchenko <andriy.shevche...@linux.intel.com>
+Date: Tue, 19 Aug 2014 20:29:14 +0300
+Subject: [PATCH 036/164] dmaengine: dw: convert dw_dma_slave to use explicit
+ HS interfaces
+
+Instead of exposing the possibility to set DMA registers CFG_HI and CFG_LO
+strict user to provide handshake interfaces explicitly.
+
+Signed-off-by: Andy Shevchenko <andriy.shevche...@linux.intel.com>
+Acked-by: Hans-Christian Egtvedt <egtv...@samfundet.no>
+Signed-off-by: Vinod Koul <vinod.k...@intel.com>
+(cherry picked from commit 7e1e2f27c5508518e58e5cbb11e26cbb815f4c56)
+Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.moha...@intel.com>
+
+Conflicts:
+ arch/avr32/mach-at32ap/at32ap700x.c
+---
+ arch/avr32/mach-at32ap/at32ap700x.c | 15 +++++----------
+ drivers/dma/dw/core.c | 4 ++--
+ include/linux/platform_data/dma-dw.h | 10 ++++------
+ 3 files changed, 11 insertions(+), 18 deletions(-)
+
+diff --git a/arch/avr32/mach-at32ap/at32ap700x.c
b/arch/avr32/mach-at32ap/at32ap700x.c
+index 1756416..2ca9e66 100644
+--- a/arch/avr32/mach-at32ap/at32ap700x.c
++++ b/arch/avr32/mach-at32ap/at32ap700x.c
+@@ -1356,10 +1356,8 @@ at32_add_device_mci(unsigned int id, struct
mci_platform_data *data)
+ goto fail;
+
+ slave->sdata.dma_dev = &dw_dmac0_device.dev;
+- slave->sdata.cfg_hi = (DWC_CFGH_SRC_PER(0)
+- | DWC_CFGH_DST_PER(1));
+- slave->sdata.cfg_lo &= ~(DWC_CFGL_HS_DST_POL
+- | DWC_CFGL_HS_SRC_POL);
++ slave->sdata.src_id = 0;
++ slave->sdata.dst_id = 1;
+
+ data->dma_slave = slave;
+
+@@ -2055,8 +2053,7 @@ at32_add_device_ac97c(unsigned int id, struct
ac97c_platform_data *data,
+ /* Check if DMA slave interface for capture should be configured. */
+ if (flags & AC97C_CAPTURE) {
+ rx_dws->dma_dev = &dw_dmac0_device.dev;
+- rx_dws->cfg_hi = DWC_CFGH_SRC_PER(3);
+- rx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
++ rx_dws->src_id = 3;
+ rx_dws->src_master = 0;
+ rx_dws->dst_master = 1;
+ }
+@@ -2064,8 +2061,7 @@ at32_add_device_ac97c(unsigned int id, struct
ac97c_platform_data *data,
+ /* Check if DMA slave interface for playback should be configured. */
+ if (flags & AC97C_PLAYBACK) {
+ tx_dws->dma_dev = &dw_dmac0_device.dev;
+- tx_dws->cfg_hi = DWC_CFGH_DST_PER(4);
+- tx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
++ tx_dws->dst_id = 4;
+ tx_dws->src_master = 0;
+ tx_dws->dst_master = 1;
+ }
+@@ -2137,8 +2133,7 @@ at32_add_device_abdac(unsigned int id, struct
atmel_abdac_pdata *data)
+ dws = &data->dws;
+
+ dws->dma_dev = &dw_dmac0_device.dev;
+- dws->cfg_hi = DWC_CFGH_DST_PER(2);
+- dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
++ dws->dst_id = 2;
+ dws->src_master = 0;
+ dws->dst_master = 1;
+
+diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
+index 80301a1..25abadd 100644
+--- a/drivers/dma/dw/core.c
++++ b/drivers/dma/dw/core.c
+@@ -155,8 +155,8 @@ static void dwc_initialize(struct dw_dma_chan *dwc)
+ */
+ BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev);
+
+- cfghi = dws->cfg_hi;
+- cfglo |= dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK;
++ cfghi |= DWC_CFGH_DST_PER(dws->dst_id);
++ cfghi |= DWC_CFGH_SRC_PER(dws->src_id);
+ } else {
+ if (dwc->direction == DMA_MEM_TO_DEV)
+ cfghi = DWC_CFGH_DST_PER(dwc->request_line);
+diff --git a/include/linux/platform_data/dma-dw.h
b/include/linux/platform_data/dma-dw.h
+index 481ab23..f2ad24b 100644
+--- a/include/linux/platform_data/dma-dw.h
++++ b/include/linux/platform_data/dma-dw.h
+@@ -18,17 +18,15 @@
+ * struct dw_dma_slave - Controller-specific information about a slave
+ *
+ * @dma_dev: required DMA master device. Depricated.
+- * @bus_id: name of this device channel, not just a device name since
+- * devices may have more than one channel e.g. "foo_tx"
+- * @cfg_hi: Platform-specific initializer for the CFG_HI register
+- * @cfg_lo: Platform-specific initializer for the CFG_LO register
++ * @src_id: src request line
++ * @dst_id: dst request line
+ * @src_master: src master for transfers on allocated channel.
+ * @dst_master: dest master for transfers on allocated channel.
+ */
+ struct dw_dma_slave {
+ struct device *dma_dev;
+- u32 cfg_hi;
+- u32 cfg_lo;
++ u8 src_id;
++ u8 dst_id;
+ u8 src_master;
+ u8 dst_master;
+ };
+--
+1.7.7.6
+
diff --git
a/features/soc/baytrail/dmaengine-dw-enable-clock-before-access.patch
b/features/soc/baytrail/dmaengine-dw-enable-clock-before-access.patch
new file mode 100644
index 0000000..3956a35
--- /dev/null
+++ b/features/soc/baytrail/dmaengine-dw-enable-clock-before-access.patch
@@ -0,0 +1,48 @@
+From 2508dcd5c8d5b9b9f4fafb44bcde6d6d04242b13 Mon Sep 17 00:00:00 2001
+From: Andy Shevchenko <andriy.shevche...@linux.intel.com>
+Date: Thu, 8 May 2014 12:01:48 +0300
+Subject: [PATCH 033/164] dmaengine: dw: enable clock before access
+
+hclk signal is a bus clock. So, it means we have to have it enabled during
+access to the DMA controller. This patch makes sure that we enable clock before
+access to the device, though it currently works on Intel hardware.
+
+Signed-off-by: Andy Shevchenko <andriy.shevche...@linux.intel.com>
+Signed-off-by: Vinod Koul <vinod.k...@intel.com>
+(cherry picked from commit d2f78e95e42a9130002c76f1a1f76e657a4b4004)
+Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.moha...@intel.com>
+---
+ drivers/dma/dw/core.c | 10 +++++-----
+ 1 files changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
+index c4fbd3e..ba8ddba 100644
+--- a/drivers/dma/dw/core.c
++++ b/drivers/dma/dw/core.c
+@@ -1491,6 +1491,11 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct
dw_dma_platform_data *pdata)
+ dw->regs = chip->regs;
+ chip->dw = dw;
+
++ dw->clk = devm_clk_get(chip->dev, "hclk");
++ if (IS_ERR(dw->clk))
++ return PTR_ERR(dw->clk);
++ clk_prepare_enable(dw->clk);
++
+ dw_params = dma_read_byaddr(chip->regs, DW_PARAMS);
+ autocfg = dw_params >> DW_PARAMS_EN & 0x1;
+
+@@ -1518,11 +1523,6 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct
dw_dma_platform_data *pdata)
+ if (!dw->chan)
+ return -ENOMEM;
+
+- dw->clk = devm_clk_get(chip->dev, "hclk");
+- if (IS_ERR(dw->clk))
+- return PTR_ERR(dw->clk);
+- clk_prepare_enable(dw->clk);
+-
+ /* Get hardware configuration parameters */
+ if (autocfg) {
+ max_blk_size = dma_readl(dw, MAX_BLK_SIZE);
+--
+1.7.7.6
+
diff --git
a/features/soc/baytrail/dmaengine-dw-fix-checkpatch.pl-warnings.patch
b/features/soc/baytrail/dmaengine-dw-fix-checkpatch.pl-warnings.patch
new file mode 100644
index 0000000..a45de80
--- /dev/null
+++ b/features/soc/baytrail/dmaengine-dw-fix-checkpatch.pl-warnings.patch
@@ -0,0 +1,40 @@
+From a2bfe9dfba7a50b4a276d3f8bec89d8d476674e5 Mon Sep 17 00:00:00 2001
+From: Wan Ahmad Zainie <wan.ahmad.zainie.wan.moha...@intel.com>
+Date: Fri, 21 Aug 2015 11:07:23 +0800
+Subject: [PATCH 151/164] dmaengine: dw: fix checkpatch.pl warnings
+
+This commit is to fix the result of running scripts/checkpatch.pl against
+0035-dmaengine-dw-move-dw_dmac.h-to-where-it-belongs-to.patch
+
+Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.moha...@intel.com>
+---
+ drivers/dma/dw/regs.h | 6 ++++--
+ 1 files changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/dma/dw/regs.h b/drivers/dma/dw/regs.h
+index 00d27a9..8f1e0fb 100644
+--- a/drivers/dma/dw/regs.h
++++ b/drivers/dma/dw/regs.h
+@@ -161,7 +161,8 @@ struct dw_dma_regs {
+ #define DWC_CTLH_DONE 0x00001000
+ #define DWC_CTLH_BLOCK_TS_MASK 0x00000fff
+
+-/* Bitfields in CFG_LO. Platform-configurable bits are in
<linux/platform_data/dma-dw.h> */
++/* Bitfields in CFG_LO.
++ * Platform-configurable bits are in <linux/platform_data/dma-dw.h> */
+ #define DWC_CFGL_CH_PRIOR_MASK (0x7 << 5) /* priority mask */
+ #define DWC_CFGL_CH_PRIOR(x) ((x) << 5) /* priority */
+ #define DWC_CFGL_CH_SUSP (1 << 8) /* pause xfer */
+@@ -172,7 +173,8 @@ struct dw_dma_regs {
+ #define DWC_CFGL_RELOAD_SAR (1 << 30)
+ #define DWC_CFGL_RELOAD_DAR (1 << 31)
+
+-/* Bitfields in CFG_HI. Platform-configurable bits are in
<linux/platform_data/dma-dw.h> */
++/* Bitfields in CFG_HI.
++ * Platform-configurable bits are in <linux/platform_data/dma-dw.h> */
+ #define DWC_CFGH_DS_UPD_EN (1 << 5)
+ #define DWC_CFGH_SS_UPD_EN (1 << 6)
+
+--
+1.7.7.6
+
diff --git
a/features/soc/baytrail/dmaengine-dw-fix-regression-in-dw_probe-function.patch
b/features/soc/baytrail/dmaengine-dw-fix-regression-in-dw_probe-function.patch
new file mode 100644
index 0000000..da1e13d
--- /dev/null
+++
b/features/soc/baytrail/dmaengine-dw-fix-regression-in-dw_probe-function.patch
@@ -0,0 +1,114 @@
+From fe77edb836d579f294b1f2c94992790e3ec44758 Mon Sep 17 00:00:00 2001
+From: Andy Shevchenko <andriy.shevche...@linux.intel.com>
+Date: Thu, 8 May 2014 12:01:49 +0300
+Subject: [PATCH 034/164] dmaengine: dw: fix regression in dw_probe() function
+
+The commit dbde5c29 "dw_dmac: use devm_* functions to simplify code" turns
+probe function to use devm_* helpers and simultaneously brings a regression.
+
+We have to 1) call clk_disable_unprepare() on error path, and 2) check error
+code of clk_enable_prepare(). First part was done in the original code, second
+one is an update.
+
+Signed-off-by: Andy Shevchenko <andriy.shevche...@linux.intel.com>
+Signed-off-by: Vinod Koul <vinod.k...@intel.com>
+(cherry picked from commit 8be4f523b48087765defd18483c66b268b3286e5)
+Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.moha...@intel.com>
+---
+ drivers/dma/dw/core.c | 33 ++++++++++++++++++++++++---------
+ 1 files changed, 24 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
+index ba8ddba..80301a1 100644
+--- a/drivers/dma/dw/core.c
++++ b/drivers/dma/dw/core.c
+@@ -1494,7 +1494,9 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct
dw_dma_platform_data *pdata)
+ dw->clk = devm_clk_get(chip->dev, "hclk");
+ if (IS_ERR(dw->clk))
+ return PTR_ERR(dw->clk);
+- clk_prepare_enable(dw->clk);
++ err = clk_prepare_enable(dw->clk);
++ if (err)
++ return err;
+
+ dw_params = dma_read_byaddr(chip->regs, DW_PARAMS);
+ autocfg = dw_params >> DW_PARAMS_EN & 0x1;
+@@ -1503,15 +1505,19 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct
dw_dma_platform_data *pdata)
+
+ if (!pdata && autocfg) {
+ pdata = devm_kzalloc(chip->dev, sizeof(*pdata), GFP_KERNEL);
+- if (!pdata)
+- return -ENOMEM;
++ if (!pdata) {
++ err = -ENOMEM;
++ goto err_pdata;
++ }
+
+ /* Fill platform data with the default values */
+ pdata->is_private = true;
+ pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING;
+ pdata->chan_priority = CHAN_PRIORITY_ASCENDING;
+- } else if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS)
+- return -EINVAL;
++ } else if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) {
++ err = -EINVAL;
++ goto err_pdata;
++ }
+
+ if (autocfg)
+ nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 0x7) + 1;
+@@ -1520,8 +1526,10 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct
dw_dma_platform_data *pdata)
+
+ dw->chan = devm_kcalloc(chip->dev, nr_channels, sizeof(*dw->chan),
+ GFP_KERNEL);
+- if (!dw->chan)
+- return -ENOMEM;
++ if (!dw->chan) {
++ err = -ENOMEM;
++ goto err_pdata;
++ }
+
+ /* Get hardware configuration parameters */
+ if (autocfg) {
+@@ -1551,7 +1559,8 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct
dw_dma_platform_data *pdata)
+ sizeof(struct dw_desc), 4, 0);
+ if (!dw->desc_pool) {
+ dev_err(chip->dev, "No memory for descriptors dma pool\n");
+- return -ENOMEM;
++ err = -ENOMEM;
++ goto err_pdata;
+ }
+
+ tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw);
+@@ -1559,7 +1568,7 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct
dw_dma_platform_data *pdata)
+ err = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED,
+ "dw_dmac", dw);
+ if (err)
+- return err;
++ goto err_pdata;
+
+ INIT_LIST_HEAD(&dw->dma.channels);
+ for (i = 0; i < nr_channels; i++) {
+@@ -1654,6 +1663,10 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct
dw_dma_platform_data *pdata)
+ dma_async_device_register(&dw->dma);
+
+ return 0;
++
++err_pdata:
++ clk_disable_unprepare(dw->clk);
++ return err;
+ }
+ EXPORT_SYMBOL_GPL(dw_dma_probe);
+
+@@ -1674,6 +1687,8 @@ int dw_dma_remove(struct dw_dma_chip *chip)
+ channel_clear_bit(dw, CH_EN, dwc->mask);
+ }
+
++ clk_disable_unprepare(dw->clk);
++
+ return 0;
+ }
+ EXPORT_SYMBOL_GPL(dw_dma_remove);
+--
+1.7.7.6
+
diff --git
a/features/soc/baytrail/dmaengine-dw-introduce-generic-filter-function.patch
b/features/soc/baytrail/dmaengine-dw-introduce-generic-filter-function.patch
new file mode 100644
index 0000000..85a60bc
--- /dev/null
+++ b/features/soc/baytrail/dmaengine-dw-introduce-generic-filter-function.patch
@@ -0,0 +1,195 @@
+From e2bc0ad33c7909de23bafe738f66e5dfc315fc45 Mon Sep 17 00:00:00 2001
+From: Andy Shevchenko <andriy.shevche...@linux.intel.com>
+Date: Tue, 19 Aug 2014 20:29:16 +0300
+Subject: [PATCH 038/164] dmaengine: dw: introduce generic filter function
+
+The introduced filter function would be reused in the ACPI and DT cases since
+in those cases we have to apply mandatory data to the requested channel. Thus,
+patch moves platform driver to use it in that case.
+
+The function unlikely can't be used by users of the driver due to an implicit
+dependency to the dw_dmac_core module.
+
+Signed-off-by: Andy Shevchenko <andriy.shevche...@linux.intel.com>
+Signed-off-by: Vinod Koul <vinod.k...@intel.com>
+(cherry picked from commit 4d130de20c3f39fc1a1aecd3969b50d49ff2e358)
+Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.moha...@intel.com>
+
+Conflicts:
+ drivers/dma/dw/platform.c
+ Due to commit
+ 1be347b dmaengine: dw: append MODULE_ALIAS for platform driver
+---
+ drivers/dma/dw/core.c | 20 ++++++++++++++
+ drivers/dma/dw/internal.h | 24 +----------------
+ drivers/dma/dw/platform.c | 63 +++++++++++++-------------------------------
+ 3 files changed, 40 insertions(+), 67 deletions(-)
+
+diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
+index 9a1eb07..91e5f22 100644
+--- a/drivers/dma/dw/core.c
++++ b/drivers/dma/dw/core.c
+@@ -915,6 +915,26 @@ err_desc_get:
+ return NULL;
+ }
+
++bool dw_dma_filter(struct dma_chan *chan, void *param)
++{
++ struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
++ struct dw_dma_slave *dws = param;
++
++ if (!dws || dws->dma_dev != chan->device->dev)
++ return false;
++
++ /* We have to copy data since dws can be temporary storage */
++
++ dwc->src_id = dws->src_id;
++ dwc->dst_id = dws->dst_id;
++
++ dwc->src_master = dws->src_master;
++ dwc->dst_master = dws->dst_master;
++
++ return true;
++}
++EXPORT_SYMBOL_GPL(dw_dma_filter);
++
+ /*
+ * Fix sconfig's burst size according to dw_dmac. We need to convert them as:
+ * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
+diff --git a/drivers/dma/dw/internal.h b/drivers/dma/dw/internal.h
+index 43cc1df..2c8d02f 100644
+--- a/drivers/dma/dw/internal.h
++++ b/drivers/dma/dw/internal.h
+@@ -43,28 +43,6 @@ int dw_dma_resume(struct dw_dma_chip *chip);
+
+ #endif /* CONFIG_PM_SLEEP */
+
+-/**
+- * dwc_get_dms - get destination master
+- * @slave: pointer to the custom slave configuration
+- *
+- * Returns destination master in the custom slave configuration if defined, or
+- * default value otherwise.
+- */
+-static inline unsigned int dwc_get_dms(struct dw_dma_slave *slave)
+-{
+- return slave ? slave->dst_master : 0;
+-}
+-
+-/**
+- * dwc_get_sms - get source master
+- * @slave: pointer to the custom slave configuration
+- *
+- * Returns source master in the custom slave configuration if defined, or
+- * default value otherwise.
+- */
+-static inline unsigned int dwc_get_sms(struct dw_dma_slave *slave)
+-{
+- return slave ? slave->src_master : 1;
+-}
++extern bool dw_dma_filter(struct dma_chan *chan, void *param);
+
+ #endif /* _DW_DMAC_INTERNAL_H */
+diff --git a/drivers/dma/dw/platform.c b/drivers/dma/dw/platform.c
+index d878d22..43122d6 100644
+--- a/drivers/dma/dw/platform.c
++++ b/drivers/dma/dw/platform.c
+@@ -25,76 +25,51 @@
+
+ #include "internal.h"
+
+-struct dw_dma_of_filter_args {
+- struct dw_dma *dw;
+- unsigned int req;
+- unsigned int src;
+- unsigned int dst;
+-};
+-
+-static bool dw_dma_of_filter(struct dma_chan *chan, void *param)
+-{
+- struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
+- struct dw_dma_of_filter_args *fargs = param;
+-
+- /* Ensure the device matches our channel */
+- if (chan->device != &fargs->dw->dma)
+- return false;
+-
+- dwc->src_id = fargs->req;
+- dwc->dst_id = fargs->req;
+- dwc->src_master = fargs->src;
+- dwc->dst_master = fargs->dst;
+-
+- return true;
+-}
+-
+ #define DRV_NAME "dw_dmac"
+
+ static struct dma_chan *dw_dma_of_xlate(struct of_phandle_args *dma_spec,
+ struct of_dma *ofdma)
+ {
+ struct dw_dma *dw = ofdma->of_dma_data;
+- struct dw_dma_of_filter_args fargs = {
+- .dw = dw,
++ struct dw_dma_slave slave = {
++ .dma_dev = dw->dma.dev,
+ };
+ dma_cap_mask_t cap;
+
+ if (dma_spec->args_count != 3)
+ return NULL;
+
+- fargs.req = dma_spec->args[0];
+- fargs.src = dma_spec->args[1];
+- fargs.dst = dma_spec->args[2];
++ slave.src_id = dma_spec->args[0];
++ slave.dst_id = dma_spec->args[0];
++ slave.src_master = dma_spec->args[1];
++ slave.dst_master = dma_spec->args[2];
+
+- if (WARN_ON(fargs.req >= DW_DMA_MAX_NR_REQUESTS ||
+- fargs.src >= dw->nr_masters ||
+- fargs.dst >= dw->nr_masters))
++ if (WARN_ON(slave.src_id >= DW_DMA_MAX_NR_REQUESTS ||
++ slave.dst_id >= DW_DMA_MAX_NR_REQUESTS ||
++ slave.src_master >= dw->nr_masters ||
++ slave.dst_master >= dw->nr_masters))
+ return NULL;
+
+ dma_cap_zero(cap);
+ dma_cap_set(DMA_SLAVE, cap);
+
+ /* TODO: there should be a simpler way to do this */
+- return dma_request_channel(cap, dw_dma_of_filter, &fargs);
++ return dma_request_channel(cap, dw_dma_filter, &slave);
+ }
+
+ #ifdef CONFIG_ACPI
+ static bool dw_dma_acpi_filter(struct dma_chan *chan, void *param)
+ {
+- struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
+ struct acpi_dma_spec *dma_spec = param;
++ struct dw_dma_slave slave = {
++ .dma_dev = dma_spec->dev,
++ .src_id = dma_spec->slave_id,
++ .dst_id = dma_spec->slave_id,
++ .src_master = 1,
++ .dst_master = 0,
++ };
+
+- if (chan->device->dev != dma_spec->dev ||
+- chan->chan_id != dma_spec->chan_id)
+- return false;
+-
+- dwc->src_id = dma_spec->slave_id;
+- dwc->dst_id = dma_spec->slave_id;
+- dwc->src_master = dwc_get_sms(NULL);
+- dwc->dst_master = dwc_get_dms(NULL);
+-
+- return true;
++ return dw_dma_filter(chan, &slave);
+ }
+
+ static void dw_dma_acpi_controller_register(struct dw_dma *dw)
+--
+1.7.7.6
+
diff --git
a/features/soc/baytrail/dmaengine-dw-move-clock-operations-to-platform.c.patch
b/features/soc/baytrail/dmaengine-dw-move-clock-operations-to-platform.c.patch
new file mode 100644
index 0000000..8736bd9
--- /dev/null
+++
b/features/soc/baytrail/dmaengine-dw-move-clock-operations-to-platform.c.patch
@@ -0,0 +1,203 @@
+From 91ec87b183fbaf9f06061957108ee2a50276b74c Mon Sep 17 00:00:00 2001
+From: Andy Shevchenko <andriy.shevche...@linux.intel.com>
+Date: Tue, 19 Aug 2014 20:29:17 +0300
+Subject: [PATCH 039/164] dmaengine: dw: move clock operations to platform.c
+
+On BayTrail platform DMA is not functional in the PCI mode, whereby it always
+failed and exit at the point when it tries to get a clock. It causes the PCI
+mode probe to exit with the error message:
+ dw_dmac_pci: probe of 0000:00:1e.0 failed with error -2
+
+This patch moves clock operations to where it belongs to. Thus, the clock is
+provided only in ACPI / non-PCI cases.
+
+Reported-by: Chew, Chiau Ee <chiau.ee.c...@intel.com>
+Signed-off-by: Andy Shevchenko <andriy.shevche...@linux.intel.com>
+Signed-off-by: Vinod Koul <vinod.k...@intel.com>
+(cherry picked from commit a15636e83eb0dedefcb1221be729023e4c281748)
+Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.moha...@intel.com>
+---
+ drivers/dma/dw/core.c | 16 ----------------
+ drivers/dma/dw/internal.h | 2 ++
+ drivers/dma/dw/platform.c | 25 ++++++++++++++++++++++---
+ drivers/dma/dw/regs.h | 1 -
+ 4 files changed, 24 insertions(+), 20 deletions(-)
+
+diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
+index 91e5f22..83a7a9c 100644
+--- a/drivers/dma/dw/core.c
++++ b/drivers/dma/dw/core.c
+@@ -11,7 +11,6 @@
+ */
+
+ #include <linux/bitops.h>
+-#include <linux/clk.h>
+ #include <linux/delay.h>
+ #include <linux/dmaengine.h>
+ #include <linux/dma-mapping.h>
+@@ -1484,13 +1483,6 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct
dw_dma_platform_data *pdata)
+ dw->regs = chip->regs;
+ chip->dw = dw;
+
+- dw->clk = devm_clk_get(chip->dev, "hclk");
+- if (IS_ERR(dw->clk))
+- return PTR_ERR(dw->clk);
+- err = clk_prepare_enable(dw->clk);
+- if (err)
+- return err;
+-
+ dw_params = dma_read_byaddr(chip->regs, DW_PARAMS);
+ autocfg = dw_params >> DW_PARAMS_EN & 0x1;
+
+@@ -1657,7 +1649,6 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct
dw_dma_platform_data *pdata)
+ return 0;
+
+ err_pdata:
+- clk_disable_unprepare(dw->clk);
+ return err;
+ }
+ EXPORT_SYMBOL_GPL(dw_dma_probe);
+@@ -1679,8 +1670,6 @@ int dw_dma_remove(struct dw_dma_chip *chip)
+ channel_clear_bit(dw, CH_EN, dwc->mask);
+ }
+
+- clk_disable_unprepare(dw->clk);
+-
+ return 0;
+ }
+ EXPORT_SYMBOL_GPL(dw_dma_remove);
+@@ -1690,7 +1679,6 @@ void dw_dma_shutdown(struct dw_dma_chip *chip)
+ struct dw_dma *dw = chip->dw;
+
+ dw_dma_off(dw);
+- clk_disable_unprepare(dw->clk);
+ }
+ EXPORT_SYMBOL_GPL(dw_dma_shutdown);
+
+@@ -1701,8 +1689,6 @@ int dw_dma_suspend(struct dw_dma_chip *chip)
+ struct dw_dma *dw = chip->dw;
+
+ dw_dma_off(dw);
+- clk_disable_unprepare(dw->clk);
+-
+ return 0;
+ }
+ EXPORT_SYMBOL_GPL(dw_dma_suspend);
+@@ -1711,9 +1697,7 @@ int dw_dma_resume(struct dw_dma_chip *chip)
+ {
+ struct dw_dma *dw = chip->dw;
+
+- clk_prepare_enable(dw->clk);
+ dma_writel(dw, CFG, DW_CFG_DMA_EN);
+-
+ return 0;
+ }
+ EXPORT_SYMBOL_GPL(dw_dma_resume);
+diff --git a/drivers/dma/dw/internal.h b/drivers/dma/dw/internal.h
+index 2c8d02f..82258a1 100644
+--- a/drivers/dma/dw/internal.h
++++ b/drivers/dma/dw/internal.h
+@@ -21,12 +21,14 @@
+ * @dev: struct device of the DMA controller
+ * @irq: irq line
+ * @regs: memory mapped I/O space
++ * @clk: hclk clock
+ * @dw: struct dw_dma that is filed by dw_dma_probe()
+ */
+ struct dw_dma_chip {
+ struct device *dev;
+ int irq;
+ void __iomem *regs;
++ struct clk *clk;
+ struct dw_dma *dw;
+ };
+
+diff --git a/drivers/dma/dw/platform.c b/drivers/dma/dw/platform.c
+index 43122d6..278b3ef 100644
+--- a/drivers/dma/dw/platform.c
++++ b/drivers/dma/dw/platform.c
+@@ -180,10 +180,17 @@ static int dw_probe(struct platform_device *pdev)
+
+ chip->dev = dev;
+
+- err = dw_dma_probe(chip, pdata);
++ chip->clk = devm_clk_get(chip->dev, "hclk");
++ if (IS_ERR(chip->clk))
++ return PTR_ERR(chip->clk);
++ err = clk_prepare_enable(chip->clk);
+ if (err)
+ return err;
+
++ err = dw_dma_probe(chip, pdata);
++ if (err)
++ goto err_dw_dma_probe;
++
+ platform_set_drvdata(pdev, chip);
+
+ if (pdev->dev.of_node) {
+@@ -198,6 +205,10 @@ static int dw_probe(struct platform_device *pdev)
+ dw_dma_acpi_controller_register(chip->dw);
+
+ return 0;
++
++err_dw_dma_probe:
++ clk_disable_unprepare(chip->clk);
++ return err;
+ }
+
+ static int dw_remove(struct platform_device *pdev)
+@@ -207,7 +218,10 @@ static int dw_remove(struct platform_device *pdev)
+ if (pdev->dev.of_node)
+ of_dma_controller_free(pdev->dev.of_node);
+
+- return dw_dma_remove(chip);
++ dw_dma_remove(chip);
++ clk_disable_unprepare(chip->clk);
++
++ return 0;
+ }
+
+ static void dw_shutdown(struct platform_device *pdev)
+@@ -215,6 +229,7 @@ static void dw_shutdown(struct platform_device *pdev)
+ struct dw_dma_chip *chip = platform_get_drvdata(pdev);
+
+ dw_dma_shutdown(chip);
++ clk_disable_unprepare(chip->clk);
+ }
+
+ #ifdef CONFIG_OF
+@@ -240,7 +255,10 @@ static int dw_suspend_noirq(struct device *dev)
+ struct platform_device *pdev = to_platform_device(dev);
+ struct dw_dma_chip *chip = platform_get_drvdata(pdev);
+
+- return dw_dma_suspend(chip);
++ dw_dma_suspend(chip);
++ clk_disable_unprepare(chip->clk);
++
++ return 0;
+ }
+
+ static int dw_resume_noirq(struct device *dev)
+@@ -248,6 +266,7 @@ static int dw_resume_noirq(struct device *dev)
+ struct platform_device *pdev = to_platform_device(dev);
+ struct dw_dma_chip *chip = platform_get_drvdata(pdev);
+
++ clk_prepare_enable(chip->clk);
+ return dw_dma_resume(chip);
+ }
+
+diff --git a/drivers/dma/dw/regs.h b/drivers/dma/dw/regs.h
+index 0e82d99..00d27a9 100644
+--- a/drivers/dma/dw/regs.h
++++ b/drivers/dma/dw/regs.h
+@@ -251,7 +251,6 @@ struct dw_dma {
+ void __iomem *regs;
+ struct dma_pool *desc_pool;
+ struct tasklet_struct tasklet;
+- struct clk *clk;
+
+ /* channels */
+ struct dw_dma_chan *chan;
+--
+1.7.7.6
+
diff --git
a/features/soc/baytrail/dmaengine-dw-move-dw_dmac.h-to-where-it-belongs-to.patch
b/features/soc/baytrail/dmaengine-dw-move-dw_dmac.h-to-where-it-belongs-to.patch
new file mode 100644
index 0000000..2af6388
--- /dev/null
+++
b/features/soc/baytrail/dmaengine-dw-move-dw_dmac.h-to-where-it-belongs-to.patch
@@ -0,0 +1,412 @@
+From 334b3b58b7ae3517a49439e4f603d760e85faa9c Mon Sep 17 00:00:00 2001
+From: Andy Shevchenko <andriy.shevche...@linux.intel.com>
+Date: Tue, 19 Aug 2014 20:29:12 +0300
+Subject: [PATCH 035/164] dmaengine: dw: move dw_dmac.h to where it belongs to
+
+There is a common storage for platform data related structures and definitions
+inside kernel source tree. The patch moves file from include/linux to
+include/linux/platform_data and renames it acoordingly. The users are also
+updated.
+
+Signed-off-by: Andy Shevchenko <andriy.shevche...@linux.intel.com>
+Acked-by: Viresh Kumar <viresh.ku...@linaro.org>
+[For the arch/avr32/.* and .*sound/atmel.*]
+Acked-by: Hans-Christian Egtvedt <egtv...@samfundet.no>
+Signed-off-by: Vinod Koul <vinod.k...@intel.com>
+
+(cherry picked from commit 3d598f47e804a77208c6bb0a454123018e2f2281)
+Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.moha...@intel.com>
+---
+ MAINTAINERS | 2 +-
+ arch/avr32/mach-at32ap/at32ap700x.c | 2 +-
+ arch/avr32/mach-at32ap/include/mach/atmel-mci.h | 2 +-
+ drivers/dma/dw/internal.h | 2 +-
+ drivers/dma/dw/regs.h | 6 +-
+ include/linux/dw_dmac.h | 114 -----------------------
+ include/linux/platform_data/dma-dw.h | 114 +++++++++++++++++++++++
+ include/sound/atmel-abdac.h | 2 +-
+ include/sound/atmel-ac97c.h | 2 +-
+ sound/atmel/abdac.c | 2 +-
+ sound/atmel/ac97c.c | 2 +-
+ 11 files changed, 125 insertions(+), 125 deletions(-)
+ delete mode 100644 include/linux/dw_dmac.h
+ create mode 100644 include/linux/platform_data/dma-dw.h
+
+diff --git a/MAINTAINERS b/MAINTAINERS
+index 900d98e..c58539e 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -7551,7 +7551,7 @@ SYNOPSYS DESIGNWARE DMAC DRIVER
+ M: Viresh Kumar <viresh.li...@gmail.com>
+ M: Andy Shevchenko <andriy.shevche...@linux.intel.com>
+ S: Maintained
+-F: include/linux/dw_dmac.h
++F: include/linux/platform_data/dma-dw.h
+ F: drivers/dma/dw/
+
+ SYNOPSYS DESIGNWARE MMC/SD/SDIO DRIVER
+diff --git a/arch/avr32/mach-at32ap/at32ap700x.c
b/arch/avr32/mach-at32ap/at32ap700x.c
+index a1f4d1e..1756416 100644
+--- a/arch/avr32/mach-at32ap/at32ap700x.c
++++ b/arch/avr32/mach-at32ap/at32ap700x.c
+@@ -7,7 +7,7 @@
+ */
+ #include <linux/clk.h>
+ #include <linux/delay.h>
+-#include <linux/dw_dmac.h>
++#include <linux/platform_data/dma-dw.h>
+ #include <linux/fb.h>
+ #include <linux/init.h>
+ #include <linux/platform_device.h>
+diff --git a/arch/avr32/mach-at32ap/include/mach/atmel-mci.h
b/arch/avr32/mach-at32ap/include/mach/atmel-mci.h
+index 4bba585..11d7f4b 100644
+--- a/arch/avr32/mach-at32ap/include/mach/atmel-mci.h
++++ b/arch/avr32/mach-at32ap/include/mach/atmel-mci.h
+@@ -1,7 +1,7 @@
+ #ifndef __MACH_ATMEL_MCI_H
+ #define __MACH_ATMEL_MCI_H
+
+-#include <linux/dw_dmac.h>
++#include <linux/platform_data/dma-dw.h>
+
+ /**
+ * struct mci_dma_data - DMA data for MCI interface
+diff --git a/drivers/dma/dw/internal.h b/drivers/dma/dw/internal.h
+index 32667f9..43cc1df 100644
+--- a/drivers/dma/dw/internal.h
++++ b/drivers/dma/dw/internal.h
+@@ -12,7 +12,7 @@
+ #define _DW_DMAC_INTERNAL_H
+
+ #include <linux/device.h>
+-#include <linux/dw_dmac.h>
++#include <linux/platform_data/dma-dw.h>
+
+ #include "regs.h"
+
+diff --git a/drivers/dma/dw/regs.h b/drivers/dma/dw/regs.h
+index bb98d3e..af02439 100644
+--- a/drivers/dma/dw/regs.h
++++ b/drivers/dma/dw/regs.h
+@@ -11,7 +11,7 @@
+
+ #include <linux/interrupt.h>
+ #include <linux/dmaengine.h>
+-#include <linux/dw_dmac.h>
++#include <linux/platform_data/dma-dw.h>
+
+ #define DW_DMA_MAX_NR_CHANNELS 8
+ #define DW_DMA_MAX_NR_REQUESTS 16
+@@ -161,7 +161,7 @@ struct dw_dma_regs {
+ #define DWC_CTLH_DONE 0x00001000
+ #define DWC_CTLH_BLOCK_TS_MASK 0x00000fff
+
+-/* Bitfields in CFG_LO. Platform-configurable bits are in <linux/dw_dmac.h> */
++/* Bitfields in CFG_LO. Platform-configurable bits are in
<linux/platform_data/dma-dw.h> */
+ #define DWC_CFGL_CH_PRIOR_MASK (0x7 << 5) /* priority mask */
+ #define DWC_CFGL_CH_PRIOR(x) ((x) << 5) /* priority */
+ #define DWC_CFGL_CH_SUSP (1 << 8) /* pause xfer */
+@@ -172,7 +172,7 @@ struct dw_dma_regs {
+ #define DWC_CFGL_RELOAD_SAR (1 << 30)
+ #define DWC_CFGL_RELOAD_DAR (1 << 31)
+
+-/* Bitfields in CFG_HI. Platform-configurable bits are in <linux/dw_dmac.h> */
++/* Bitfields in CFG_HI. Platform-configurable bits are in
<linux/platform_data/dma-dw.h> */
+ #define DWC_CFGH_DS_UPD_EN (1 << 5)
+ #define DWC_CFGH_SS_UPD_EN (1 << 6)
+
+diff --git a/include/linux/dw_dmac.h b/include/linux/dw_dmac.h
+deleted file mode 100644
+index 481ab23..0000000
+--- a/include/linux/dw_dmac.h
++++ /dev/null
+@@ -1,114 +0,0 @@
+-/*
+- * Driver for the Synopsys DesignWare DMA Controller (aka DMACA on
+- * AVR32 systems.)
+- *
+- * Copyright (C) 2007 Atmel Corporation
+- * Copyright (C) 2010-2011 ST Microelectronics
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+- */
+-#ifndef DW_DMAC_H
+-#define DW_DMAC_H
+-
+-#include <linux/dmaengine.h>
+-
+-/**
+- * struct dw_dma_slave - Controller-specific information about a slave
+- *
+- * @dma_dev: required DMA master device. Depricated.
+- * @bus_id: name of this device channel, not just a device name since
+- * devices may have more than one channel e.g. "foo_tx"
+- * @cfg_hi: Platform-specific initializer for the CFG_HI register
+- * @cfg_lo: Platform-specific initializer for the CFG_LO register
+- * @src_master: src master for transfers on allocated channel.
+- * @dst_master: dest master for transfers on allocated channel.
+- */
+-struct dw_dma_slave {
+- struct device *dma_dev;
+- u32 cfg_hi;
+- u32 cfg_lo;
+- u8 src_master;
+- u8 dst_master;
+-};
+-
+-/**
+- * struct dw_dma_platform_data - Controller configuration parameters
+- * @nr_channels: Number of channels supported by hardware (max 8)
+- * @is_private: The device channels should be marked as private and not for
+- * by the general purpose DMA channel allocator.
+- * @chan_allocation_order: Allocate channels starting from 0 or 7
+- * @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0.
+- * @block_size: Maximum block size supported by the controller
+- * @nr_masters: Number of AHB masters supported by the controller
+- * @data_width: Maximum data width supported by hardware per AHB master
+- * (0 - 8bits, 1 - 16bits, ..., 5 - 256bits)
+- * @sd: slave specific data. Used for configuring channels
+- * @sd_count: count of slave data structures passed.
+- */
+-struct dw_dma_platform_data {
+- unsigned int nr_channels;
+- bool is_private;
+-#define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */
+-#define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */
+- unsigned char chan_allocation_order;
+-#define CHAN_PRIORITY_ASCENDING 0 /* chan0 highest */
+-#define CHAN_PRIORITY_DESCENDING 1 /* chan7 highest */
+- unsigned char chan_priority;
+- unsigned short block_size;
+- unsigned char nr_masters;
+- unsigned char data_width[4];
+-};
+-
+-/* bursts size */
+-enum dw_dma_msize {
+- DW_DMA_MSIZE_1,
+- DW_DMA_MSIZE_4,
+- DW_DMA_MSIZE_8,
+- DW_DMA_MSIZE_16,
+- DW_DMA_MSIZE_32,
+- DW_DMA_MSIZE_64,
+- DW_DMA_MSIZE_128,
+- DW_DMA_MSIZE_256,
+-};
+-
+-/* Platform-configurable bits in CFG_HI */
+-#define DWC_CFGH_FCMODE (1 << 0)
+-#define DWC_CFGH_FIFO_MODE (1 << 1)
+-#define DWC_CFGH_PROTCTL(x) ((x) << 2)
+-#define DWC_CFGH_SRC_PER(x) ((x) << 7)
+-#define DWC_CFGH_DST_PER(x) ((x) << 11)
+-
+-/* Platform-configurable bits in CFG_LO */
+-#define DWC_CFGL_LOCK_CH_XFER (0 << 12) /* scope of LOCK_CH */
+-#define DWC_CFGL_LOCK_CH_BLOCK (1 << 12)
+-#define DWC_CFGL_LOCK_CH_XACT (2 << 12)
+-#define DWC_CFGL_LOCK_BUS_XFER (0 << 14) /* scope of LOCK_BUS */
+-#define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14)
+-#define DWC_CFGL_LOCK_BUS_XACT (2 << 14)
+-#define DWC_CFGL_LOCK_CH (1 << 15) /* channel lockout */
+-#define DWC_CFGL_LOCK_BUS (1 << 16) /* busmaster lockout */
+-#define DWC_CFGL_HS_DST_POL (1 << 18) /* dst handshake active low */
+-#define DWC_CFGL_HS_SRC_POL (1 << 19) /* src handshake active low */
+-
+-/* DMA API extensions */
+-struct dw_cyclic_desc {
+- struct dw_desc **desc;
+- unsigned long periods;
+- void (*period_callback)(void *param);
+- void *period_callback_param;
+-};
+-
+-struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
+- dma_addr_t buf_addr, size_t buf_len, size_t period_len,
+- enum dma_transfer_direction direction);
+-void dw_dma_cyclic_free(struct dma_chan *chan);
+-int dw_dma_cyclic_start(struct dma_chan *chan);
+-void dw_dma_cyclic_stop(struct dma_chan *chan);
+-
+-dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan);
+-
+-dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan);
+-
+-#endif /* DW_DMAC_H */
+diff --git a/include/linux/platform_data/dma-dw.h
b/include/linux/platform_data/dma-dw.h
+new file mode 100644
+index 0000000..481ab23
+--- /dev/null
++++ b/include/linux/platform_data/dma-dw.h
+@@ -0,0 +1,114 @@
++/*
++ * Driver for the Synopsys DesignWare DMA Controller (aka DMACA on
++ * AVR32 systems.)
++ *
++ * Copyright (C) 2007 Atmel Corporation
++ * Copyright (C) 2010-2011 ST Microelectronics
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#ifndef DW_DMAC_H
++#define DW_DMAC_H
++
++#include <linux/dmaengine.h>
++
++/**
++ * struct dw_dma_slave - Controller-specific information about a slave
++ *
++ * @dma_dev: required DMA master device. Depricated.
++ * @bus_id: name of this device channel, not just a device name since
++ * devices may have more than one channel e.g. "foo_tx"
++ * @cfg_hi: Platform-specific initializer for the CFG_HI register
++ * @cfg_lo: Platform-specific initializer for the CFG_LO register
++ * @src_master: src master for transfers on allocated channel.
++ * @dst_master: dest master for transfers on allocated channel.
++ */
++struct dw_dma_slave {
++ struct device *dma_dev;
++ u32 cfg_hi;
++ u32 cfg_lo;
++ u8 src_master;
++ u8 dst_master;
++};
++
++/**
++ * struct dw_dma_platform_data - Controller configuration parameters
++ * @nr_channels: Number of channels supported by hardware (max 8)
++ * @is_private: The device channels should be marked as private and not for
++ * by the general purpose DMA channel allocator.
++ * @chan_allocation_order: Allocate channels starting from 0 or 7
++ * @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0.
++ * @block_size: Maximum block size supported by the controller
++ * @nr_masters: Number of AHB masters supported by the controller
++ * @data_width: Maximum data width supported by hardware per AHB master
++ * (0 - 8bits, 1 - 16bits, ..., 5 - 256bits)
++ * @sd: slave specific data. Used for configuring channels
++ * @sd_count: count of slave data structures passed.
++ */
++struct dw_dma_platform_data {
++ unsigned int nr_channels;
++ bool is_private;
++#define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */
++#define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */
++ unsigned char chan_allocation_order;
++#define CHAN_PRIORITY_ASCENDING 0 /* chan0 highest */
++#define CHAN_PRIORITY_DESCENDING 1 /* chan7 highest */
++ unsigned char chan_priority;
++ unsigned short block_size;
++ unsigned char nr_masters;
++ unsigned char data_width[4];
++};
++
++/* bursts size */
++enum dw_dma_msize {
++ DW_DMA_MSIZE_1,
++ DW_DMA_MSIZE_4,
++ DW_DMA_MSIZE_8,
++ DW_DMA_MSIZE_16,
++ DW_DMA_MSIZE_32,
++ DW_DMA_MSIZE_64,
++ DW_DMA_MSIZE_128,
++ DW_DMA_MSIZE_256,
++};
++
++/* Platform-configurable bits in CFG_HI */
++#define DWC_CFGH_FCMODE (1 << 0)
++#define DWC_CFGH_FIFO_MODE (1 << 1)
++#define DWC_CFGH_PROTCTL(x) ((x) << 2)
++#define DWC_CFGH_SRC_PER(x) ((x) << 7)
++#define DWC_CFGH_DST_PER(x) ((x) << 11)
++
++/* Platform-configurable bits in CFG_LO */
++#define DWC_CFGL_LOCK_CH_XFER (0 << 12) /* scope of LOCK_CH */
++#define DWC_CFGL_LOCK_CH_BLOCK (1 << 12)
++#define DWC_CFGL_LOCK_CH_XACT (2 << 12)
++#define DWC_CFGL_LOCK_BUS_XFER (0 << 14) /* scope of LOCK_BUS */
++#define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14)
++#define DWC_CFGL_LOCK_BUS_XACT (2 << 14)
++#define DWC_CFGL_LOCK_CH (1 << 15) /* channel lockout */
++#define DWC_CFGL_LOCK_BUS (1 << 16) /* busmaster lockout */
++#define DWC_CFGL_HS_DST_POL (1 << 18) /* dst handshake active low */
++#define DWC_CFGL_HS_SRC_POL (1 << 19) /* src handshake active low */
++
++/* DMA API extensions */
++struct dw_cyclic_desc {
++ struct dw_desc **desc;
++ unsigned long periods;
++ void (*period_callback)(void *param);
++ void *period_callback_param;
++};
++
++struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
++ dma_addr_t buf_addr, size_t buf_len, size_t period_len,
++ enum dma_transfer_direction direction);
++void dw_dma_cyclic_free(struct dma_chan *chan);
++int dw_dma_cyclic_start(struct dma_chan *chan);
++void dw_dma_cyclic_stop(struct dma_chan *chan);
++
++dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan);
++
++dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan);
++
++#endif /* DW_DMAC_H */
+diff --git a/include/sound/atmel-abdac.h b/include/sound/atmel-abdac.h
+index edff6a8..a8f735d 100644
+--- a/include/sound/atmel-abdac.h
++++ b/include/sound/atmel-abdac.h
+@@ -10,7 +10,7 @@
+ #ifndef __INCLUDE_SOUND_ATMEL_ABDAC_H
+ #define __INCLUDE_SOUND_ATMEL_ABDAC_H
+
+-#include <linux/dw_dmac.h>
++#include <linux/platform_data/dma-dw.h>
+
+ /**
+ * struct atmel_abdac_pdata - board specific ABDAC configuration
+diff --git a/include/sound/atmel-ac97c.h b/include/sound/atmel-ac97c.h
+index e6aabdb..31979c4 100644
+--- a/include/sound/atmel-ac97c.h
++++ b/include/sound/atmel-ac97c.h
+@@ -10,7 +10,7 @@
+ #ifndef __INCLUDE_SOUND_ATMEL_AC97C_H
+ #define __INCLUDE_SOUND_ATMEL_AC97C_H
+
+-#include <linux/dw_dmac.h>
++#include <linux/platform_data/dma-dw.h>
+
+ #define AC97C_CAPTURE 0x01
+ #define AC97C_PLAYBACK 0x02
+diff --git a/sound/atmel/abdac.c b/sound/atmel/abdac.c
+index 3519518..412403b 100644
+--- a/sound/atmel/abdac.c
++++ b/sound/atmel/abdac.c
+@@ -9,7 +9,7 @@
+ */
+ #include <linux/clk.h>
+ #include <linux/bitmap.h>
+-#include <linux/dw_dmac.h>
++#include <linux/platform_data/dma-dw.h>
+ #include <linux/dmaengine.h>
+ #include <linux/dma-mapping.h>
+ #include <linux/init.h>
+diff --git a/sound/atmel/ac97c.c b/sound/atmel/ac97c.c
+index c5f0ddd..e005849 100644
+--- a/sound/atmel/ac97c.c
++++ b/sound/atmel/ac97c.c
+@@ -31,7 +31,7 @@
+ #include <sound/atmel-ac97c.h>
+ #include <sound/memalloc.h>
+
+-#include <linux/dw_dmac.h>
++#include <linux/platform_data/dma-dw.h>
+
+ #include <mach/cpu.h>
+
+--
+1.7.7.6
+
--
1.9.1
--
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