From: Sangeetha Rao <sangeetha....@intel.com>
This patch updates the fix to PPC476 erratum 48 in order to use the
correct calculation for L2 cache register for CPUs 4 and 5.
Signed-off-by: Sangeetha Rao <sangeetha....@intel.com>
---
arch/powerpc/kernel/traps.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index b4b4048..cc036fb 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -866,8 +866,8 @@ void machine_check_exception(struct pt_regs *regs)
mtdcr((cpu + 3) * 256, 0x304);
l2plbstats1 = mfdcr((cpu + 3) * 256 + 4);
} else {
- mtdcr((cpu + 9)*256, 0x304);
- l2plbstats1 = mfdcr((cpu + 9) * 256 + 4);
+ mtdcr((cpu + 15) * 256, 0x304);
+ l2plbstats1 = mfdcr((cpu + 15) * 256 + 4);
}
if (((mcsr & 0x80200000) == 0x80200000) &&
@@ -879,7 +879,7 @@ void machine_check_exception(struct pt_regs *regs)
mtdcr((cpu + 3) * 256 + 4,
0x000C0000);
} else {
- mtdcr((cpu + 9) * 256 + 4,
+ mtdcr((cpu + 15) * 256 + 4,
0x000C0000);
}
printk(KERN_INFO "machine_check_exception: Core %d: MCSR=0x%x
l2plbstats1=0x%x",
--
1.7.9.5
--
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