From: "Chew, Chiau Ee" <chiau.ee.c...@intel.com>
BYT ACPI mode SPI not read/writing correctly at low speeds
using DMA mode. Fix the issue by changing DMA SRC_MSIZE and
DEST_MSIZE of SPI FIFO side from 16 to 32.
Signed-off-by: Chew, Chiau Ee <chiau.ee.c...@intel.com>
Signed-off-by: Maurice Petallo <mauricex.r.peta...@intel.com>
---
drivers/spi/spi-pxa2xx-dma.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/spi-pxa2xx-dma.c b/drivers/spi/spi-pxa2xx-dma.c
index 3c0b551..79515ed 100644
--- a/drivers/spi/spi-pxa2xx-dma.c
+++ b/drivers/spi/spi-pxa2xx-dma.c
@@ -385,7 +385,7 @@ int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data
*chip,
* otherwise we use the default. Also we use the default FIFO
* thresholds for now.
*/
- *burst_code = chip_info ? chip_info->dma_burst_size : 16;
+ *burst_code = chip_info ? chip_info->dma_burst_size : 32;
*threshold = SSCR1_RxTresh(RX_THRESH_DFLT)
| SSCR1_TxTresh(TX_THRESH_DFLT);
--
1.9.1
--
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