From: Paul Butler <paul.but...@windriver.com>
Add the rapidio device to the powerpc tree
Add the rapidio support for the powerpc 44x lsi board
Signed-off-by: Paul Butler <paul.but...@windriver.com>
---
arch/powerpc/boot/dts/lsi_acp342x.dts | 317 +++++++++++++++++++++++++++++
arch/powerpc/boot/dts/lsi_acp344x.dts | 355 +++++++++++++++++++++++++++++++++
arch/powerpc/include/asm/axxia-rio.h | 103 ++++++++++
arch/powerpc/include/asm/rio.h | 41 ++++
arch/powerpc/platforms/44x/Makefile | 3 +-
arch/powerpc/platforms/44x/acprio.c | 65 ++++++
arch/powerpc/platforms/44x/acpx1.c | 1 +
7 files changed, 884 insertions(+), 1 deletion(-)
create mode 100644 arch/powerpc/boot/dts/lsi_acp342x.dts
create mode 100644 arch/powerpc/boot/dts/lsi_acp344x.dts
create mode 100644 arch/powerpc/include/asm/axxia-rio.h
create mode 100644 arch/powerpc/platforms/44x/acprio.c
diff --git a/arch/powerpc/boot/dts/lsi_acp342x.dts
b/arch/powerpc/boot/dts/lsi_acp342x.dts
new file mode 100644
index 0000000..da6066e
--- /dev/null
+++ b/arch/powerpc/boot/dts/lsi_acp342x.dts
@@ -0,0 +1,317 @@
+/*
+ * Device Tree Source for IBM Embedded PPC 476 Platform
+ *
+ * Copyright 2009 Torez Smith, IBM Corporation.
+ *
+ * Based on earlier code:
+ * Copyright (c) 2006, 2007 IBM Corp.
+ * Josh Boyer <jwbo...@linux.vnet.ibm.com>, David Gibson <d...@au1.ibm.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+/memreserve/ 0x00000000 0x00400000;
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ model = "ibm,acpx1-4xx";
+ compatible = "ibm,acpx1-4xx","ibm,47x-AMP";
+ dcr-parent = <&{/cpus/cpu@0}>;
+
+ aliases {
+ serial0 = &UART0;
+ serial1 = &UART1;
+ rapidio0 = &rio0;
+ ethernet0 = &FEMAC;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ model = "PowerPC,4xx"; // real CPU changed in sim
+ reg = <0>;
+ clock-frequency = <0x5f5e1000>;
+ timebase-frequency = <0x5f5e1000>;
+ i-cache-line-size = <32>;
+ d-cache-line-size = <32>;
+ i-cache-size = <32768>;
+ d-cache-size = <32768>;
+ dcr-controller;
+ dcr-access-method = "native";
+ status = "ok";
+ reset-type = <3>; // 1=core, 2=chip, 3=system (default)
+ };
+ cpu@1 {
+ device_type = "cpu";
+ model = "PowerPC,4xx"; // real CPU changed in sim
+ reg = <1>;
+ clock-frequency = <0x5f5e1000>;
+ timebase-frequency = <0x5f5e1000>;
+ i-cache-line-size = <32>;
+ d-cache-line-size = <32>;
+ i-cache-size = <32768>;
+ d-cache-size = <32768>;
+ dcr-controller;
+ dcr-access-method = "native";
+ status = "disabled";
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x2040>;
+ reset-type = <3>; // 1=core, 2=chip, 3=system (default)
+ };
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x00000000 0x10000000>;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x00000000 0x00000000 0x00000000>;
+ };
+
+ MPIC: interrupt-controller {
+ compatible = "chrp,open-pic";
+ interrupt-controller;
+ dcr-reg = <0xffc00000 0x00030000>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ pic-no-reset;
+ };
+
+ plb {
+ /* Could be PLB6, doesn't matter */
+ compatible = "ibm,plb-4xx", "ibm,plb4";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+ clock-frequency = <0>; // Filled in by zImage
+
+ POB0: opb {
+ compatible = "ibm,opb-4xx", "ibm,opb";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ /* Wish there was a nicer way of specifying a full
32-bit
+ range */
+ ranges = <0x00000000 0x00000020 0x00000000 0x80000000
+ 0x80000000 0x00000020 0x80000000 0x80000000>;
+ clock-frequency = <0>; // Filled in by zImage
+ UART0: serial@00404000 {
+ device_type = "serial";
+ compatible = "acp-uart0";
+ enabled = <1>;
+ reg = <0x00404000 0x1000>;
+ clock-reg = <0x00408040 0x20>;
+ clock-frequency = <200000000>;
+ current-speed = <9600>;
+ interrupt-parent = <&MPIC>;
+ interrupts = <22>;
+ };
+ UART1: serial@00405000 {
+ device_type = "serial";
+ compatible = "acp-uart1";
+ enabled = <0>;
+ reg = <0x00405000 0x1000>;
+ clock-reg = <0x00408060 0x20>;
+ clock-frequency = <200000000>;
+ current-speed = <9600>;
+ interrupt-parent = <&MPIC>;
+ interrupts = <23>;
+ };
+ USB0: usb@004a4000 {
+ device_type = "usb";
+ compatible = "acp-usb";
+ enabled = <0>;
+ reg = <0x004a4000 0x00020000>;
+ interrupt-parent = <&MPIC>;
+ interrupts = <31>;
+ };
+ I2C: i2c@00403000 {
+ compatible = "acp-i2c";
+ enabled = <0>;
+ reg = <0x00403000 0x00001000>;
+ interrupt-parent = <&MPIC>;
+ interrupts = <21>;
+ };
+ SSP: ssp@00402000 {
+ compatible = "acp-ssp";
+ enabled = <0>;
+ reg = <0x00402000 0x00001000>;
+ interrupt-parent = <&MPIC>;
+ interrupts = <20>;
+ };
+ NAND: nand@00440000 {
+ device_type = "nand";
+ compatible = "acp-nand";
+ enabled = <1>;
+ reg = <0x00440000 0x20000
+ 0x0040c000 0x1000>;
+ };
+ FEMAC: femac@00480000 {
+ device_type = "network";
+ compatible = "acp-femac";
+ enabled = <1>;
+ reg = <0x00480000 0x1000
+ 0x00481000 0x1000
+ 0x00482000 0x1000>;
+ interrupt-parent = <&MPIC>;
+ interrupts = <33>;
+ mdio-reg = <0x00409000 0x1000>;
+ // The following will get filled in by
+ // the boot loader.
+ mdio-clock = <0>;
+ phy-address = <0>;
+ ad-value = <0>;
+ mac-address = [00 00 00 00 00 00];
+ };
+ };
+ };
+
+
+ nvrtc {
+ compatible = "ds1743-nvram", "ds1743", "rtc-ds1743";
+ reg = <0 0xEF703000 0x2000>;
+ };
+
+ system {
+ ncr_0x00a_0x010_0x0002c = <0>; // filled in by the boot loader.
+ ncr_0x016_0x0ff_0x00010 = <0>; // filled in by the boot loader.
+ };
+
+ chosen {
+ linux,stdout-path = "/plb/opb/serial@00404000";
+ };
+
+ PCIE0: pciex@f00c0000 {
+ compatible = "lsi,plb-pciex";
+ device_type = "pci";
+ enabled = <0>;
+ plx = <0>;
+ primary;
+ port = <0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ /* config space access MPAGE7 registers*/
+ reg = <0x0020 0x78000000 0x01000000
+ 0x0020 0x004c0000 0x00008000 >;
+ bus-range = <0 0x0f>;
+ /* Outbound ranges */
+ /* < <3-cell PCI addr> <2-cell CPU (PLB) addr> <2-cell size> >
*/
+ ranges = <0x02000000 0x00000000 0xa0000000
+ 0x20 0x40000000
+ 0x00 0x10000000>;
+ /* Inbound ranges */
+ /* < <3-cell PCI addr> <2-cell CPU addr> <2-cell size> > */
+ dma-ranges = <0x02000000 0x00000000 0x00000000
+ 0x00 0x00000000
+ 0x00 0x10000000>;
+ interrupt-parent = <&MPIC>;
+ interrupts = <29 2>;
+ interrupt-map-mask = <0000 0 0 7>;
+ interrupt-map = <
+ /* <3-cell dev> <irq#> <prnt> <2-cell prnt IRQ/sense>
*/
+ 0000 0 0 1 &MPIC 29 2
+ 0000 0 0 2 &MPIC 29 2
+ 0000 0 0 3 &MPIC 29 2
+ 0000 0 0 4 &MPIC 29 2
+ >;
+ };
+
+ PCIE1: pciex@f00c8000 {
+ compatible = "lsi,plb-pciex";
+ device_type = "pci";
+ enabled = <0>;
+ plx = <0>;
+ primary;
+ port = <1>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ /* config space access MPAGE7 registers*/
+ reg = <0x0020 0xf8000000 0x01000000
+ 0x0020 0x004c8000 0x00008000 >;
+ bus-range = <0 0x0f>;
+ /* Outbound ranges */
+ /* < <3-cell PCI addr> <2-cell CPU (PLB) addr> <2-cell size> >
*/
+ ranges = <0x02000000 0x00000000 0xb0000000
+ 0x20 0xc0000000
+ 0x00 0x10000000>;
+ /* Inbound ranges */
+ /* < <3-cell PCI addr> <2-cell CPU addr> <2-cell size> > */
+ dma-ranges = <0x02000000 0x00000000 0x00000000
+ 0x00 0x00000000
+ 0x00 0x10000000>;
+ interrupt-parent = <&MPIC>;
+ interrupts = <72 2>;
+ interrupt-map-mask = <0000 0 0 7>;
+ interrupt-map = <
+ /* <3-cell dev> <irq#> <prnt> <2-cell prnt IRQ/sense>
*/
+ 0000 0 0 1 &MPIC 72 2
+ 0000 0 0 2 &MPIC 72 2
+ 0000 0 0 3 &MPIC 72 2
+ 0000 0 0 4 &MPIC 72 2
+ >;
+ };
+
+ PCIE2: pciex@f00d0000 {
+ compatible = "lsi,plb-pciex";
+ device_type = "pci";
+ enabled = <0>;
+ plx = <0>;
+ primary;
+ port = <2>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ /* config space access MPAGE7 registers*/
+ reg = <0x0021 0x38000000 0x01000000
+ 0x0020 0x004d0000 0x00008000 >;
+ bus-range = <0 0x0f>;
+ /* Outbound ranges */
+ /* < <3-cell PCI addr> <2-cell CPU (PLB) addr> <2-cell size> >
*/
+ ranges = <0x02000000 0x00000000 0xc0000000
+ 0x21 0x00000000
+ 0x00 0x10000000>;
+ /* Inbound ranges */
+ /* < <3-cell PCI addr> <2-cell CPU addr> <2-cell size> > */
+ dma-ranges = <0x02000000 0x00000000 0x00000000
+ 0x00 0x00000000
+ 0x00 0x10000000>;
+
+ interrupt-parent = <&MPIC>;
+ interrupts = <73 2>;
+ interrupt-map-mask = <0000 0 0 7>;
+ interrupt-map = <
+ /* <3-cell dev> <irq#> <prnt> <2-cell prnt IRQ/sense>
*/
+ 0000 0 0 1 &MPIC 73 2
+ 0000 0 0 2 &MPIC 73 2
+ 0000 0 0 3 &MPIC 73 2
+ 0000 0 0 4 &MPIC 73 2
+ >;
+ };
+
+ rio0: rapidio {
+ index = <0>;
+ status = "ok";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "acp,rapidio-delta";
+ device_type = "rapidio";
+ reg = <0x0020 0x00420000 0x1000>; /* SRIO Conf region */
+ ranges = <0x0 0x0 0x0020 0x80000000 0x0 0x40000000>;
+ interrupt-parent = <&MPIC>;
+ interrupts = <30 0x2 /* NCP_INTR_MPIC_SRC_AXIS_SRIO */>;
+ outb-dmes = <2 0x00000003 1 0x00000000>; /* X7 Defect 44844 */
+ };
+
+};
diff --git a/arch/powerpc/boot/dts/lsi_acp344x.dts
b/arch/powerpc/boot/dts/lsi_acp344x.dts
new file mode 100644
index 0000000..63d49f5
--- /dev/null
+++ b/arch/powerpc/boot/dts/lsi_acp344x.dts
@@ -0,0 +1,355 @@
+/*
+ * Device Tree Source for IBM Embedded PPC 476 Platform
+ *
+ * Copyright 2009 Torez Smith, IBM Corporation.
+ *
+ * Based on earlier code:
+ * Copyright (c) 2006, 2007 IBM Corp.
+ * Josh Boyer <jwbo...@linux.vnet.ibm.com>, David Gibson <d...@au1.ibm.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+/memreserve/ 0x00000000 0x00400000;
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ model = "ibm,acpx1-4xx";
+ compatible = "ibm,acpx1-4xx","ibm,47x-AMP";
+ dcr-parent = <&{/cpus/cpu@0}>;
+
+ aliases {
+ serial0 = &UART0;
+ serial1 = &UART1;
+ rapidio0 = &rio0;
+ ethernet0 = &FEMAC;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ model = "PowerPC,4xx"; // real CPU changed in sim
+ reg = <0>;
+ clock-frequency = <0x5f5e1000>;
+ timebase-frequency = <0x5f5e1000>;
+ i-cache-line-size = <32>;
+ d-cache-line-size = <32>;
+ i-cache-size = <32768>;
+ d-cache-size = <32768>;
+ dcr-controller;
+ dcr-access-method = "native";
+ status = "ok";
+ reset-type = <3>; // 1=core, 2=chip, 3=system (default)
+ };
+ cpu@1 {
+ device_type = "cpu";
+ model = "PowerPC,4xx"; // real CPU changed in sim
+ reg = <1>;
+ clock-frequency = <0x5f5e1000>;
+ timebase-frequency = <0x5f5e1000>;
+ i-cache-line-size = <32>;
+ d-cache-line-size = <32>;
+ i-cache-size = <32768>;
+ d-cache-size = <32768>;
+ dcr-controller;
+ dcr-access-method = "native";
+ status = "disabled";
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x2040>;
+ reset-type = <3>; // 1=core, 2=chip, 3=system (default)
+ };
+ cpu@2 {
+ device_type = "cpu";
+ model = "PowerPC,4xx"; // real CPU changed in sim
+ reg = <2>;
+ clock-frequency = <0x5f5e1000>;
+ timebase-frequency = <0x5f5e1000>;
+ i-cache-line-size = <32>;
+ d-cache-line-size = <32>;
+ i-cache-size = <32768>;
+ d-cache-size = <32768>;
+ dcr-controller;
+ dcr-access-method = "native";
+ status = "disabled";
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x2080>;
+ reset-type = <3>; // 1=core, 2=chip, 3=system (default)
+ };
+ cpu@3 {
+ device_type = "cpu";
+ model = "PowerPC,4xx"; // real CPU changed in sim
+ reg = <3>;
+ clock-frequency = <0x5f5e1000>;
+ timebase-frequency = <0x5f5e1000>;
+ i-cache-line-size = <32>;
+ d-cache-line-size = <32>;
+ i-cache-size = <32768>;
+ d-cache-size = <32768>;
+ dcr-controller;
+ dcr-access-method = "native";
+ status = "disabled";
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20c0>;
+ reset-type = <3>; // 1=core, 2=chip, 3=system (default)
+ };
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x00000000 0x80000000>; // filled in by
U-Boot
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x00000000 0x80000000 0x80000000>; // filled in by
U-Boot
+ };
+
+ MPIC: interrupt-controller {
+ compatible = "chrp,open-pic";
+ interrupt-controller;
+ dcr-reg = <0xffc00000 0x00030000>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ pic-no-reset;
+ };
+
+ plb {
+ /* Could be PLB6, doesn't matter */
+ compatible = "ibm,plb-4xx", "ibm,plb4";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+ clock-frequency = <0>; // Filled in by zImage
+
+ POB0: opb {
+ compatible = "ibm,opb-4xx", "ibm,opb";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ /* Wish there was a nicer way of specifying a full
32-bit
+ range */
+ ranges = <0x00000000 0x00000020 0x00000000 0x80000000
+ 0x80000000 0x00000020 0x80000000 0x80000000>;
+ clock-frequency = <0>; // Filled in by zImage
+ UART0: serial@00404000 {
+ device_type = "serial";
+ compatible = "acp-uart0";
+ enabled = <1>;
+ reg = <0x00404000 0x1000>;
+ clock-reg = <0x00408040 0x20>;
+ clock-frequency = <0xbebc200>;
+ current-speed = <9600>;
+ interrupt-parent = <&MPIC>;
+ interrupts = <22>;
+ };
+ UART1: serial@00405000 {
+ device_type = "serial";
+ compatible = "acp-uart1";
+ enabled = <0>;
+ reg = <0x00405000 0x1000>;
+ clock-reg = <0x00408060 0x20>;
+ clock-frequency = <200000000>;
+ current-speed = <9600>;
+ interrupt-parent = <&MPIC>;
+ interrupts = <23>;
+ };
+ USB0: usb@004a4000 {
+ device_type = "usb";
+ compatible = "acp-usb";
+ enabled = <0>;
+ reg = <0x004a4000 0x00020000>;
+ interrupt-parent = <&MPIC>;
+ interrupts = <31>;
+ };
+ I2C: i2c@00403000 {
+ compatible = "acp-i2c";
+ enabled = <0>;
+ reg = <0x00403000 0x00001000>;
+ interrupt-parent = <&MPIC>;
+ interrupts = <21>;
+ };
+ SSP: ssp@00402000 {
+ compatible = "acp-ssp";
+ enabled = <0>;
+ reg = <0x00402000 0x00001000>;
+ interrupt-parent = <&MPIC>;
+ interrupts = <20>;
+ };
+ NAND: nand@00440000 {
+ device_type = "nand";
+ compatible = "acp-nand";
+ enabled = <1>;
+ reg = <0x00440000 0x20000
+ 0x0040c000 0x1000>;
+ };
+ FEMAC: femac@00480000 {
+ device_type = "network";
+ compatible = "acp-femac";
+ enabled = <1>;
+ reg = <0x00480000 0x1000
+ 0x00481000 0x1000
+ 0x00482000 0x1000>;
+ interrupt-parent = <&MPIC>;
+ interrupts = <33>;
+ mdio-reg = <0x00409000 0x1000>;
+ // The following will get filled in by
+ // the boot loader.
+ mdio-clock = <0>;
+ phy-address = <0>;
+ ad-value = <0>;
+ mac-address = [00 00 00 00 00 00];
+ };
+ };
+ };
+
+
+ nvrtc {
+ compatible = "ds1743-nvram", "ds1743", "rtc-ds1743";
+ reg = <0 0xEF703000 0x2000>;
+ };
+
+ system {
+ ncr_0x00a_0x010_0x0002c = <0>; // filled in by the boot loader.
+ ncr_0x016_0x0ff_0x00010 = <0>; // filled in by the boot loader.
+ };
+
+ chosen {
+ linux,stdout-path = "/plb/opb/serial@00404000";
+ };
+
+ PCIE0: pciex@f00c0000 {
+ compatible = "lsi,plb-pciex";
+ device_type = "pci";
+ enabled = <0>;
+ plx = <0>;
+ primary;
+ port = <0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ /* config space access MPAGE7 registers*/
+ reg = < 0x0020 0x78000000 0x01000000
+ 0x0020 0x004c0000 0x00008000 >;
+ bus-range = <0 0x0f>;
+ /* Outbound ranges */
+ /* < <3-cell PCI addr> <2-cell CPU (PLB) addr> <2-cell size> >
*/
+ ranges = <0x02000000 0x00000000 0xa0000000
+ 0x20 0x40000000
+ 0x00 0x10000000>;
+ /* Inbound ranges */
+ /* < <3-cell PCI addr> <2-cell CPU addr> <2-cell size> > */
+ dma-ranges = <0x02000000 0x00000000 0x00000000
+ 0x00 0x00000000
+ 0x00 0x10000000>;
+ interrupt-parent = <&MPIC>;
+ interrupts = <29 2>;
+ interrupt-map-mask = <0000 0 0 7>;
+ interrupt-map = <
+ /* <3-cell dev> <irq#> <prnt> <2-cell prnt IRQ/sense>
*/
+ 0000 0 0 1 &MPIC 29 2
+ 0000 0 0 2 &MPIC 29 2
+ 0000 0 0 3 &MPIC 29 2
+ 0000 0 0 4 &MPIC 29 2
+ >;
+ };
+
+ PCIE1: pciex@f00c8000 {
+ compatible = "lsi,plb-pciex";
+ device_type = "pci";
+ enabled = <0>;
+ plx = <0>;
+ primary;
+ port = <1>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ /* config space access MPAGE7 registers*/
+ reg = <0x0020 0xf8000000 0x01000000
+ 0x0020 0x004c8000 0x00008000 >;
+ bus-range = <0 0x0f>;
+ /* Outbound ranges */
+ /* < <3-cell PCI addr> <2-cell CPU (PLB) addr> <2-cell size> >
*/
+ ranges = <0x02000000 0x00000000 0xa0000000
+ 0x20 0xc0000000
+ 0x00 0x10000000>;
+ /* Inbound ranges */
+ /* < <3-cell PCI addr> <2-cell CPU addr> <2-cell size> > */
+ dma-ranges = <0x02000000 0x00000000 0x00000000
+ 0x00 0x00000000
+ 0x00 0x10000000>;
+ interrupt-parent = <&MPIC>;
+ interrupts = <72 2>;
+ interrupt-map-mask = <0000 0 0 7>;
+ interrupt-map = <
+ /* <3-cell dev> <irq#> <prnt> <2-cell prnt IRQ/sense>
*/
+ 0000 0 0 1 &MPIC 72 2
+ 0000 0 0 2 &MPIC 72 2
+ 0000 0 0 3 &MPIC 72 2
+ 0000 0 0 4 &MPIC 72 2
+ >;
+ };
+
+ PCIE2: pciex@f00d0000 {
+ compatible = "lsi,plb-pciex";
+ device_type = "pci";
+ enabled = <0>;
+ plx = <0>;
+ primary;
+ port = <2>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ /* config space access MPAGE7 registers*/
+ reg = <0x0021 0x38000000 0x01000000
+ 0x0020 0x004d0000 0x00008000 >;
+ bus-range = <0 0x0f>;
+ /* Outbound ranges */
+ /* < <3-cell PCI addr> <2-cell CPU (PLB) addr> <2-cell size> >
*/
+ ranges = <0x02000000 0x00000000 0xa0000000
+ 0x21 0x00000000
+ 0x00 0x10000000>;
+ /* Inbound ranges */
+ /* < <3-cell PCI addr> <2-cell CPU addr> <2-cell size> > */
+ dma-ranges = <0x02000000 0x00000000 0x00000000
+ 0x00 0x00000000
+ 0x00 0x10000000>;
+
+ interrupt-parent = <&MPIC>;
+ interrupts = <73 2>;
+ interrupt-map-mask = <0000 0 0 7>;
+ interrupt-map = <
+ /* <3-cell dev> <irq#> <prnt> <2-cell prnt IRQ/sense>
*/
+ 0000 0 0 1 &MPIC 73 2
+ 0000 0 0 2 &MPIC 73 2
+ 0000 0 0 3 &MPIC 73 2
+ 0000 0 0 4 &MPIC 73 2
+ >;
+ };
+
+ rio0: rapidio@f0020000{
+ index = <0>;
+ status = "ok";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ compatible = "acp,rapidio-delta";
+ device_type = "rapidio";
+ reg = <0x0020 0x00420000 0x1000>; /* SRIO Conf region */
+ ranges = <0x0 0x0 0x0020 0x80000000 0x0 0x40000000>;
+ interrupt-parent = <&MPIC>;
+ interrupts = <30 0x2 /* NCP_INTR_MPIC_SRC_AXIS_SRIO */>;
+ outb-dmes = <2 0x00000003 1 0x00000000>; /* X7 Defect 44844 */
+ enable_ds = <1>;
+ inb-dse = <0x00000020 0x00000400 0x00000100>; /* virt_m, data,
dbuf */
+ /* inb-dse = <0x00000002 0x00000020 0x00000020>; */
+ outb-dse = <0x00000010 0x00000400 0x00000400 0x00000010>;
/*dse,hdr,data,dbuf */
+ /* outb-dse = <0x00000002 0x00000020 0x00000020 0x00000020>; */
+ };
+};
diff --git a/arch/powerpc/include/asm/axxia-rio.h
b/arch/powerpc/include/asm/axxia-rio.h
new file mode 100644
index 0000000..2d18ee1
--- /dev/null
+++ b/arch/powerpc/include/asm/axxia-rio.h
@@ -0,0 +1,103 @@
+/*
+ * RapidIO support for LSI Axxia 3400 parts
+ *
+ */
+#ifndef __ASM_AXXIA_RIO_H__
+#define __ASM_AXXIA_RIO_H__
+
+/* Constants, Macros, etc. */
+
+#define AXXIA_RIO_SYSMEM_BARRIER() __asm__ __volatile__("msync")
+
+#define AXXIA_RIO_DISABLE_MACHINE_CHECK() \
+ {
\
+ mtmsr(mfmsr() & ~(MSR_ME)); \
+ __asm__ __volatile__("msync"); \
+ }
+
+#define AXXIA_RIO_ENABLE_MACHINE_CHECK() \
+ {
\
+ mtmsr(mfmsr() | (MSR_ME)); \
+ __asm__ __volatile__("msync"); \
+ }
+
+#define AXXIA_RIO_IF_MACHINE_CHECK(mcsr) \
+ {
\
+ __asm__ __volatile__("msync"); \
+ mcsr = mfspr(SPRN_MCSR); \
+ if (mcsr != 0) {
\
+ /* machine check would have occurred ! */
\
+ /* clear it */
\
+ mtspr(SPRN_MCSR, 0);
\
+ __asm__ __volatile__("msync");
\
+ } }
+
+#define __acp_read_rio_config(x, addr, err, op) \
+ __asm__ __volatile__( \
+ "msync" "\n" \
+ "0: "op" %1,0(%2)\n" \
+ "1: sync\n" \
+ "2: nop\n" \
+ "3:\n" \
+ ".section .fixup,\"ax\"\n" \
+ "4: li %1,-1\n" \
+ " li %0,%3\n" \
+ " b 3b\n" \
+ ".previous\n" \
+ ".section __ex_table,\"a\"\n" \
+ PPC_LONG_ALIGN "\n" \
+ PPC_LONG "0b,4b\n" \
+ PPC_LONG "1b,4b\n" \
+ PPC_LONG "2b,4b\n" \
+ ".previous" \
+ : "=r" (err), "=r" (x) \
+ : "b" (addr), "i" (-EFAULT), "0" (err))
+
+#define IN_SRIO8(a, v, ec) __acp_read_rio_config(v, a, ec, "lbz")
+#define IN_SRIO16(a, v, ec) __acp_read_rio_config(v, a, ec, "lhz")
+#define IN_SRIO32(a, v, ec) __acp_read_rio_config(v, a, ec, "lwz")
+
+#define OUT_SRIO8(a, v) out_8((u8 *) a, v)
+#define OUT_SRIO16(a, v) out_be16((u16 *) a, v)
+#define OUT_SRIO32(a, v) out_be32((u32 *) a, v)
+
+#define CORRECT_GRIO(a) __le32_to_cpu(a)
+#define CORRECT_RAB(a) (a)
+
+
+/* ACP RIO board-specific stuff */
+
+extern int axxia_rio_apio_enable(struct rio_mport *mport, u32 mask, u32 bits);
+extern int axxia_rio_apio_disable(struct rio_mport *mport);
+extern int axxia_rio_rpio_enable(struct rio_mport *mport, u32 mask, u32 bits);
+extern int axxia_rio_rpio_disable(struct rio_mport *mport);
+
+#define axxia_rapidio_board_init(v) (0)
+
+
+/*****************************/
+/* ACP RIO operational stuff */
+/*****************************/
+
+/**
+ * CNTLZW - Count leading zeros word
+ * @val: value from which count number of leading zeros
+ *
+ * Return: number of zeros
+ */
+static inline u32 CNTLZW(u32 val)
+{
+ u32 tmp = 0;
+ (void)val;
+
+ __asm__ volatile
+ (
+ " cntlzw %0,%1"
+ : /*outputs*/ "=r" (tmp)
+ : /*inputs*/ "r" (val)
+ );
+
+ return tmp;
+}
+
+#endif /* __ASM_AXXIA_RIO_H__ */
diff --git a/arch/powerpc/include/asm/rio.h b/arch/powerpc/include/asm/rio.h
index b1d2dec..02b920c 100644
--- a/arch/powerpc/include/asm/rio.h
+++ b/arch/powerpc/include/asm/rio.h
@@ -14,10 +14,51 @@
#define ASM_PPC_RIO_H
extern void platform_rio_init(void);
+
#ifdef CONFIG_FSL_RIO
extern int fsl_rio_mcheck_exception(struct pt_regs *);
#else
static inline int fsl_rio_mcheck_exception(struct pt_regs *regs) {return 0; }
#endif
+extern int axxia_rio_mcheck_exception(struct pt_regs *regs);
+
+#define DEF_RIO_IN_BE(name, size, op) \
+ static inline int name(u##size * dst, \
+ const volatile u##size __iomem *addr) \
+ { \
+ int err = 0; \
+ __asm__ __volatile__( \
+ "msync" "\n" \
+ "0:" op "%U2%X2 %1,%2\n" \
+ "1: sync\n" \
+ "2: nop\n" \
+ "3:\n" \
+ ".section .fixup,\"ax\"\n" \
+ "4: li %0,%3\n" \
+ " b 3b\n" \
+ ".previous\n" \
+ ".section __ex_table,\"a\"\n" \
+ PPC_LONG_ALIGN "\n" \
+ PPC_LONG "0b,4b\n" \
+ PPC_LONG "1b,4b\n" \
+ PPC_LONG "2b,4b\n" \
+ ".previous" \
+ : "=r" (err), "=r" (*dst) \
+ : "m" (*addr), "i" (-EFAULT), "0" (err) \
+ : "memory"); \
+ return err; \
+ }
+
+DEF_RIO_IN_BE(rio_in_8, 8, "lbz")
+DEF_RIO_IN_BE(rio_in_be16, 16, "lhz")
+DEF_RIO_IN_BE(rio_in_be32, 32, "lwz")
+
+
+/* Bit definitions for the MCSR. */
+/* Error or system error reported through the L2 cache */
+#define PPC47x_MCSR_L2 0x00200000
+#define PPC47x_MCSR_DCR 0x00100000 /* DCR timeout */
+
+
#endif /* ASM_PPC_RIO_H */
diff --git a/arch/powerpc/platforms/44x/Makefile
b/arch/powerpc/platforms/44x/Makefile
index a527e89..5ccfc48 100644
--- a/arch/powerpc/platforms/44x/Makefile
+++ b/arch/powerpc/platforms/44x/Makefile
@@ -11,4 +11,5 @@ obj-$(CONFIG_XILINX_ML510) += virtex_ml510.o
obj-$(CONFIG_ISS4xx) += iss4xx.o
obj-$(CONFIG_CANYONLANDS)+= canyonlands.o
obj-$(CONFIG_CURRITUCK) += currituck.o
-obj-$(CONFIG_ACP) += acpx1.o acpclock.o
\ No newline at end of file
+obj-$(CONFIG_ACP) += acpx1.o acpclock.o
+obj-$(CONFIG_AXXIA_RIO) += acprio.o
diff --git a/arch/powerpc/platforms/44x/acprio.c
b/arch/powerpc/platforms/44x/acprio.c
new file mode 100644
index 0000000..3c553edd
--- /dev/null
+++ b/arch/powerpc/platforms/44x/acprio.c
@@ -0,0 +1,65 @@
+/*
+ * arch/powerpc/platforms/44x/acprio.c
+ *
+ * Support for the RIO module on LSI Axxia boards
+ *
+ * Copyright (C) 2013 LSI
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/dma-mapping.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <linux/rio.h>
+#include <linux/rio_drv.h>
+#include <linux/of_platform.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/kfifo.h>
+#include <linux/dmapool.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+#include <linux/uaccess.h>
+
+#include <asm/axxia-rio.h>
+
+
+int axxia_rio_mcheck_exception(struct pt_regs *regs)
+{
+ const struct exception_table_entry *entry;
+ u32 mcsr = mfspr(SPRN_MCSR);
+
+ if (mcsr & (PPC47x_MCSR_IPR | PPC47x_MCSR_L2)) {
+ entry = search_exception_tables(regs->nip);
+ if (entry) {
+ pr_debug("(%s): Recoverable exception %lx\n",
+ __func__, regs->nip);
+ regs->msr |= MSR_RI;
+ regs->nip = entry->fixup;
+ mcsr &= ~(PPC47x_MCSR_IPR | PPC47x_MCSR_L2);
+ if (mcsr == MCSR_MCS)
+ mcsr &= ~MCSR_MCS;
+ mtspr(SPRN_MCSR, mcsr);
+ return 1;
+ }
+ }
+ return 0;
+}
+EXPORT_SYMBOL_GPL(axxia_rio_mcheck_exception);
diff --git a/arch/powerpc/platforms/44x/acpx1.c
b/arch/powerpc/platforms/44x/acpx1.c
index b903787..df93e06 100644
--- a/arch/powerpc/platforms/44x/acpx1.c
+++ b/arch/powerpc/platforms/44x/acpx1.c
@@ -46,6 +46,7 @@ static __initdata struct of_device_id acpx14xx_of_bus[] = {
{ .compatible = "ibm,plb6", },
{ .compatible = "ibm,opb", },
{ .compatible = "ibm,ebc", },
+ { .compatible = "axxia,rapidio-delta", },
{ .compatible = "acp,rapidio-delta", },
{},
};
--
1.7.9.5
--
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