From: Anders Berg anders.b...@lsi.com
Adjusted the controller setup to meet the timing requirements for I2C fast-mode
on the SCL signal (tLOW and tHIGH). For fast-mode, a 33/66 duty cycle of the
SCL is used to match the minimum timing requirements of 1.3/0.6 for tLOW/tHIGH.
Signed-off-by: Anders
From: Anders Berg anders.b...@lsi.com
Adjusted the controller setup to meet the timing requirements for I2C fast-mode
on the SCL signal (tLOW and tHIGH). For fast-mode, a 33/66 duty cycle of the
SCL is used to match the minimum timing requirements of 1.3/0.6 for tLOW/tHIGH.
Signed-off-by: Anders
