The MinnowBoard pch_gbe support is now in standard/base, no need
to apply it here.
Signed-off-by: Darren Hart <dvh...@linux.intel.com>
---
meta/cfg/kernel-cache/bsp/minnow/minnow.scc | 1 -
.../minnow/pch_gbe-Add-MinnowBoard-support.patch | 212 --------------------
2 files changed, 213 deletions(-)
delete mode 100644
meta/cfg/kernel-cache/bsp/minnow/pch_gbe-Add-MinnowBoard-support.patch
diff --git a/meta/cfg/kernel-cache/bsp/minnow/minnow.scc
b/meta/cfg/kernel-cache/bsp/minnow/minnow.scc
index 8c55a8f..5da7464 100644
--- a/meta/cfg/kernel-cache/bsp/minnow/minnow.scc
+++ b/meta/cfg/kernel-cache/bsp/minnow/minnow.scc
@@ -23,4 +23,3 @@ patch gpio-sch-Add-sch_gpio_resume_set_enable.patch
patch minnowboard-Add-base-platform-driver-for-the-MinnowB.patch
patch minnowboard-gpio-Export-MinnowBoard-expansion-GPIO.patch
patch minnowboard-keys-Bind-MinnowBoard-buttons-to-arrow-k.patch
-patch pch_gbe-Add-MinnowBoard-support.patch
diff --git
a/meta/cfg/kernel-cache/bsp/minnow/pch_gbe-Add-MinnowBoard-support.patch
b/meta/cfg/kernel-cache/bsp/minnow/pch_gbe-Add-MinnowBoard-support.patch
deleted file mode 100644
index d73e6ae..0000000
--- a/meta/cfg/kernel-cache/bsp/minnow/pch_gbe-Add-MinnowBoard-support.patch
+++ /dev/null
@@ -1,212 +0,0 @@
-From b688fe510d9eaadb2274855a826bbe4605546452 Mon Sep 17 00:00:00 2001
-From: Darren Hart <dvh...@linux.intel.com>
-Date: Sat, 18 May 2013 14:46:00 -0700
-Subject: [PATCH 5/7] pch_gbe: Add MinnowBoard support
-
-The MinnowBoard uses an AR803x PHY with the PCH GBE.
-
-It does not implement the RGMII 2ns TX clock delay in the trace routing
-nor via strapping. Add a detection method for the board and the PHY and
-enable the tx clock delay via the registers.
-
-This PHY will hibernate without link for 10 seconds. Ensure the PHY is
-awake for probe and then disable hibernation. A future improvement would
-be to convert pch_gbe to using PHYLIB and making sure we can wake the
-PHY at the necessary times rather than permanently disabling it.
-
-Unfortunately, the board does not provide a unique PCI device ID. The
-the minnow_detect() function fills the gap comparing DMI_BOARD_NAME. It
-is admittedly sub-optimal.
-
-Signed-off-by: Darren Hart <dvh...@linux.intel.com>
----
- drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h | 2 +
- .../net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c | 12 +++
- .../net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.c | 89 ++++++++++++++++++++
- .../net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.h | 2 +
- 4 files changed, 105 insertions(+)
-
-diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
-index 7fb7e17..bd4e0c5 100644
---- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
-+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
-@@ -384,6 +384,7 @@ struct pch_gbe_mac_info {
- * @revision: PHY's revision
- * @reset_delay_us: HW reset delay time[us]
- * @autoneg_advertised: Autoneg advertised
-+ * @tx_clk_delay: Setup TX clock delay in the PHY
- */
- struct pch_gbe_phy_info {
- u32 addr;
-@@ -391,6 +392,7 @@ struct pch_gbe_phy_info {
- u32 revision;
- u32 reset_delay_us;
- u16 autoneg_advertised;
-+ bool tx_clk_delay;
- };
-
- /*!
-diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
-index 8adeb4d..f487ad7 100644
---- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
-+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
-@@ -23,6 +23,8 @@
- #include <linux/module.h>
- #include <linux/net_tstamp.h>
- #include <linux/ptp_classify.h>
-+#include <linux/gpio.h>
-+#include <linux/minnowboard.h>
-
- #define DRV_VERSION "1.01"
- const char pch_driver_version[] = DRV_VERSION;
-@@ -2601,6 +2603,13 @@ static int pch_gbe_probe(struct pci_dev *pdev,
-
- pci_set_drvdata(pdev, netdev);
- adapter = netdev_priv(netdev);
-+
-+ adapter->hw.phy.tx_clk_delay = false;
-+ if (minnow_detect()) {
-+ adapter->hw.phy.tx_clk_delay = true;
-+ minnow_phy_reset();
-+ }
-+
- adapter->netdev = netdev;
- adapter->pdev = pdev;
- adapter->hw.back = adapter;
-@@ -2684,6 +2693,9 @@ static int pch_gbe_probe(struct pci_dev *pdev,
-
- dev_dbg(&pdev->dev, "PCH Network Connection\n");
-
-+ /* Disable hibernation on certain PHYs */
-+ pch_gbe_phy_disable_hibernate(&adapter->hw);
-+
- device_set_wakeup_enable(&pdev->dev, 1);
- return 0;
-
-diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.c
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.c
-index 28bb960..bb8d8b4 100644
---- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.c
-+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.c
-@@ -20,6 +20,7 @@
-
- #include "pch_gbe.h"
- #include "pch_gbe_phy.h"
-+#include <linux/gpio.h>
-
- #define PHY_MAX_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
-
-@@ -74,6 +75,15 @@
- #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
- #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
-
-+/* AR8031 PHY Debug Registers */
-+#define PHY_AR803X_ID 0x00001374
-+#define PHY_AR8031_DBG_OFF 0x1D
-+#define PHY_AR8031_DBG_DAT 0x1E
-+#define PHY_AR8031_SERDES 0x05
-+#define PHY_AR8031_HIBERNATE 0x0B
-+#define PHY_AR8031_SERDES_TX_CLK_DLY 0x0100 /* TX clock delay of 2.0ns */
-+#define PHY_AR8031_PS_HIB_EN 0x8000 /* Hibernate enable */
-+
- /* Phy Id Register (word 2) */
- #define PHY_REVISION_MASK 0x000F
-
-@@ -271,4 +281,83 @@ void pch_gbe_phy_init_setting(struct pch_gbe_hw *hw)
- mii_reg |= PHYSP_CTRL_ASSERT_CRS_TX;
- pch_gbe_phy_write_reg_miic(hw, PHY_PHYSP_CONTROL, mii_reg);
-
-+ /* Setup a TX clock delay for certain boards */
-+ if (hw->phy.tx_clk_delay)
-+ pch_gbe_phy_tx_clk_delay(hw);
-+}
-+
-+/**
-+ * pch_gbe_phy_tx_clk_delay - Setup TX clock delay via the PHY
-+ * @hw: Pointer to the HW structure
-+ * Returns
-+ * 0: Successful.
-+ * -EINVAL: Invalid argument.
-+ */
-+int pch_gbe_phy_tx_clk_delay(struct pch_gbe_hw *hw)
-+{
-+ /*
-+ * The RGMII interface requires a ~2ns TX clock delay. This is typically
-+ * done in layout with a longer trace or via PHY strapping, but can also
-+ * be done via PHY configuration registers.
-+ */
-+ u16 mii_reg;
-+ int ret = 0;
-+
-+ switch (hw->phy.id) {
-+ case PHY_AR803X_ID:
-+ pch_gbe_phy_read_reg_miic(hw, PHY_AR8031_DBG_OFF, &mii_reg);
-+ ret = pch_gbe_phy_write_reg_miic(hw, PHY_AR8031_DBG_OFF,
-+ PHY_AR8031_SERDES);
-+ if (ret)
-+ break;
-+
-+ pch_gbe_phy_read_reg_miic(hw, PHY_AR8031_DBG_DAT, &mii_reg);
-+ mii_reg |= PHY_AR8031_SERDES_TX_CLK_DLY;
-+ ret = pch_gbe_phy_write_reg_miic(hw, PHY_AR8031_DBG_DAT,
-+ mii_reg);
-+ break;
-+ default:
-+ pr_err("Unknown PHY (%x), could not set TX clock delay.\n",
-+ hw->phy.id);
-+ return -EINVAL;
-+ }
-+
-+ if (ret)
-+ pr_err("Could not configure tx clock delay for PHY.\n");
-+ return ret;
-+}
-+
-+/**
-+ * pch_gbe_phy_disable_hibernate - Disable the PHY low power state
-+ * @hw: Pointer to the HW structure
-+ * Returns
-+ * 0: Successful.
-+ * -EINVAL: Invalid argument.
-+ */
-+int pch_gbe_phy_disable_hibernate(struct pch_gbe_hw *hw)
-+{
-+ u16 mii_reg;
-+ int ret = 0;
-+
-+ switch (hw->phy.id) {
-+ case PHY_AR803X_ID:
-+ ret = pch_gbe_phy_write_reg_miic(hw, PHY_AR8031_DBG_OFF,
-+ PHY_AR8031_HIBERNATE);
-+ if (ret)
-+ break;
-+
-+ pch_gbe_phy_read_reg_miic(hw, PHY_AR8031_DBG_DAT, &mii_reg);
-+ mii_reg &= ~PHY_AR8031_PS_HIB_EN;
-+ ret = pch_gbe_phy_write_reg_miic(hw, PHY_AR8031_DBG_DAT,
-+ mii_reg);
-+ break;
-+ default:
-+ pr_err("Unknown PHY (%x), could not disable hibernation\n",
-+ hw->phy.id);
-+ return -EINVAL;
-+ }
-+
-+ if (ret)
-+ pr_err("Could not disable PHY hibernation.\n");
-+ return ret;
- }
-diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.h
b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.h
-index 03264dc..e3e4bc9 100644
---- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.h
-+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_phy.h
-@@ -33,5 +33,7 @@ void pch_gbe_phy_power_up(struct pch_gbe_hw *hw);
- void pch_gbe_phy_power_down(struct pch_gbe_hw *hw);
- void pch_gbe_phy_set_rgmii(struct pch_gbe_hw *hw);
- void pch_gbe_phy_init_setting(struct pch_gbe_hw *hw);
-+int pch_gbe_phy_tx_clk_delay(struct pch_gbe_hw *hw);
-+int pch_gbe_phy_disable_hibernate(struct pch_gbe_hw *hw);
-
- #endif /* _PCH_GBE_PHY_H_ */
---
-1.7.10.4
-
--
1.7.9.5
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