From: John Jacques <john.jacq...@lsi.com>
In some cases, the differences between simulation, emulation,
and hardware are important. This patch updates the device trees
to indicate the correct name and the arch/arm/mach-axxia code
to use it.
Signed-off-by: John Jacques <john.jacq...@lsi.com>
---
arch/arm/boot/dts/axm55xxemu.dts | 25 +---
arch/arm/boot/dts/axm55xxemu7.dts | 217 +++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/axm55xxsim.dts | 2 +-
arch/arm/boot/dts/axm55xxsim16.dts | 2 +-
arch/arm/mach-axxia/axxia.c | 3 +-
arch/arm/mach-axxia/ddr_retention.c | 33 ++++--
6 files changed, 247 insertions(+), 35 deletions(-)
create mode 100644 arch/arm/boot/dts/axm55xxemu7.dts
diff --git a/arch/arm/boot/dts/axm55xxemu.dts b/arch/arm/boot/dts/axm55xxemu.dts
index 1b22b33..93222c1 100644
--- a/arch/arm/boot/dts/axm55xxemu.dts
+++ b/arch/arm/boot/dts/axm55xxemu.dts
@@ -24,7 +24,7 @@
/ {
model = "AXM5516";
- compatible = "arm", "lsi,axm5516";
+ compatible = "arm", "lsi,axm5516-emu";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
@@ -68,29 +68,6 @@
reg = <3>;
cpu-release-addr = <0>; // Fixed by the boot loader
};
-
- /*
- cpu@4 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <4>;
- cpu-release-addr = <0>; // Fixed by the boot loader
- };
-
- cpu@5 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <5>;
- cpu-release-addr = <0>; // Fixed by the boot loader
- };
-
- cpu@6 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <6>;
- cpu-release-addr = <0>; // Fixed by the boot loader
- };
- */
};
clocks {
diff --git a/arch/arm/boot/dts/axm55xxemu7.dts
b/arch/arm/boot/dts/axm55xxemu7.dts
new file mode 100644
index 0000000..6da4393
--- /dev/null
+++ b/arch/arm/boot/dts/axm55xxemu7.dts
@@ -0,0 +1,217 @@
+/*
+ * arch/arm/boot/dts/axm55xxemu7.dts
+ *
+ * Copyright (C) 2012 LSI
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+/dts-v1/;
+
+/memreserve/ 0x00000000 0x00400000;
+
+/ {
+ model = "AXM5516";
+ compatible = "arm", "lsi,axm5516-emu";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen { };
+
+ aliases {
+ serial0 = &axxia_serial0;
+ timer = &axxia_timers;
+ ethernet0 = &axxia_femac0;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ cpu-release-addr = <0>; // Fixed by the boot loader
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ cpu-release-addr = <0>; // Fixed by the boot loader
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <2>;
+ cpu-release-addr = <0>; // Fixed by the boot loader
+ };
+
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <3>;
+ cpu-release-addr = <0>; // Fixed by the boot loader
+ };
+
+ cpu@4 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <4>;
+ cpu-release-addr = <0>; // Fixed by the boot loader
+ };
+
+ cpu@5 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <5>;
+ cpu-release-addr = <0>; // Fixed by the boot loader
+ };
+
+ cpu@6 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <6>;
+ cpu-release-addr = <0>; // Fixed by the boot loader
+ };
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu {
+ frequency = <0>; /* Filled in by the boot loader. */
+ };
+
+ peripheral {
+ frequency = <0>; /* Filled in by the boot loader. */
+ };
+
+ emmc {
+ frequency = <0>; /* Filled in by the boot loader. */
+ };
+ };
+
+ memory@00000000 {
+ device_type = "memory";
+ reg = <0 0x00000000 0 0x10000000>;
+ };
+
+ gic: interrupt-controller@2001001000 {
+ compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x20 0x01001000 0 0x1000>, /* gic dist base */
+ <0x20 0x01002000 0 0x100>, /* gic cpu base */
+ <0x20 0x10030000 0 0x100>, /* axm IPI mask reg base */
+ <0x20 0x10040000 0 0x20000>; /* axm IPI send reg base */
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <1 13 0xf08>,
+ <1 14 0xf08>;
+ };
+
+
+ gpdma@2020140000 {
+ compatible = "lsi,dma32";
+ reg = <0x20 0x20140000 0x00 0x1000>;
+ interrupts = <0 60 4>, /* busy */
+ <0 61 4>; /* error */
+
+ channel0 {
+ interrupts = <0 62 4>;
+ };
+
+ channel1 {
+ interrupts = <0 63 4>;
+ };
+ };
+
+ gpdma@2020141000 {
+ status = "disabled";
+ compatible = "lsi,dma32";
+ reg = <0x20 0x20141000 0x00 0x1000>;
+ interrupts = <0 64 4>, /* busy */
+ <0 65 4>; /* error */
+
+ channel0 {
+ interrupts = <0 66 4>;
+ };
+
+ channel1 {
+ interrupts = <0 67 4>;
+ };
+ };
+
+ gpreg@2010094000 {
+ compatible = "lsi,gpreg";
+ reg = <0x20 0x10094000 0 0x1000>;
+ };
+
+ axxia_femac0: femac@0x2010120000 {
+ compatible = "lsi,acp-femac";
+ device_type = "network";
+ reg = <0x20 0x10120000 0 0x1000>,
+ <0x20 0x10121000 0 0x1000>,
+ <0x20 0x10122000 0 0x1000>;
+ interrupts = <0 2 4>,
+ <0 3 4>,
+ <0 4 4>;
+ mdio-reg = <0x20 0x10090000 0 0x1000>;
+ mdio-clock = <0>;
+ phy-address = <0x3>;
+ ad-value = <0x61>;
+ mac-address = [00 00 00 00 00 00];
+ };
+
+ amba {
+ compatible = "arm,amba-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ axxia_serial0: uart@2010080000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x20 0x10080000 0x00 0x1000>;
+ interrupts = <0 56 4>;
+ };
+
+ axxia_timers: timer@2010091000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x20 0x10091000 0 0x1000>;
+ interrupts = <0 46 4>,
+ <0 47 4>,
+ <0 48 4>,
+ <0 49 4>,
+ <0 50 4>,
+ <0 51 4>,
+ <0 52 4>,
+ <0 53 4>;
+ };
+ };
+};
+
+/*
+ Local Variables:
+ mode: C
+ End:
+*/
diff --git a/arch/arm/boot/dts/axm55xxsim.dts b/arch/arm/boot/dts/axm55xxsim.dts
index 5620dcb..b20b09a 100644
--- a/arch/arm/boot/dts/axm55xxsim.dts
+++ b/arch/arm/boot/dts/axm55xxsim.dts
@@ -1,5 +1,5 @@
/*
- * arch/arm/boot/dts/axm-sim.dts
+ * arch/arm/boot/dts/axm55xxsim.dts
*
* Copyright (C) 2012 LSI
*
diff --git a/arch/arm/boot/dts/axm55xxsim16.dts
b/arch/arm/boot/dts/axm55xxsim16.dts
index 0b6277a..0ce2ff4 100644
--- a/arch/arm/boot/dts/axm55xxsim16.dts
+++ b/arch/arm/boot/dts/axm55xxsim16.dts
@@ -1,5 +1,5 @@
/*
- * arch/arm/boot/dts/axm-sim.dts
+ * arch/arm/boot/dts/axm55xxsim16.dts
*
* Copyright (C) 2012 LSI
*
diff --git a/arch/arm/mach-axxia/axxia.c b/arch/arm/mach-axxia/axxia.c
index 526ec98..af85305 100644
--- a/arch/arm/mach-axxia/axxia.c
+++ b/arch/arm/mach-axxia/axxia.c
@@ -58,8 +58,9 @@
extern void axxia_ddr_retention_init(void);
static const char *axxia_dt_match[] __initconst = {
- "lsi,axm5516",
"lsi,axm5516-sim",
+ "lsi,axm5516-emu",
+ "lsi,axm5516",
NULL
};
diff --git a/arch/arm/mach-axxia/ddr_retention.c
b/arch/arm/mach-axxia/ddr_retention.c
index a17f970..7e4687d 100644
--- a/arch/arm/mach-axxia/ddr_retention.c
+++ b/arch/arm/mach-axxia/ddr_retention.c
@@ -34,6 +34,7 @@
static void __iomem *nca;
static void __iomem *apb;
static void __iomem *dickens;
+static int ddr_retention_enabled;
unsigned long ncp_caal_regions_acp55xx[] = {
NCP_REGION_ID(0x0b, 0x05), /* SPPV2 */
@@ -253,6 +254,11 @@ initiate_retention_reset(void)
unsigned long value;
unsigned long delay;
+ if (0 == ddr_retention_enabled) {
+ pr_info("DDR Retention Reset is Not Enabled\n");
+ return;
+ }
+
if (NULL == nca || NULL == apb || NULL == dickens)
BUG();
@@ -330,15 +336,26 @@ static const struct file_operations proc_ops = {
void
axxia_ddr_retention_init(void)
{
- if (!of_find_compatible_node(NULL, NULL, "lsi,axm5516"))
- return;
+ /*
+ Only available on ASIC systems.
+ */
- if (!proc_create(PROC_PATH, S_IWUSR, NULL, &proc_ops)) {
- pr_err("Failed to register DDR retention proc interface\n");
- return;
+ if (of_find_compatible_node(NULL, NULL, "lsi,axm5516")) {
+ /* Create /proc entry. */
+ if (!proc_create("driver/axxia_ddr_retention_reset",
+ S_IWUSR, NULL,
+ &proc_ops)) {
+ pr_info("Failed to register DDR retention proc
entry\n");
+ } else {
+ apb = ioremap(0x2010000000, 0x40000);
+ nca = ioremap(0x002020100000ULL, 0x20000);
+ dickens = ioremap(0x2000000000, 0x1000000);
+ ddr_retention_enabled = 1;
+ pr_info("DDR Retention Reset Initialized\n");
+ }
+ } else {
+ pr_info("DDR Retention Reset is Not Available\n");
}
- apb = ioremap(0x2010000000, 0x40000);
- nca = ioremap(0x002020100000ULL, 0x20000);
- dickens = ioremap(0x2000000000, 0x1000000);
+ return;
}
--
1.7.9.5
--
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