From: Ong Boon Leong <boon.leong....@intel.com> this commit enables the following: - setup clock tree for PCI mode SPI, DMA and PWM host as the controller drivers require clock information during device/driver probe - register SPI slave
Signed-off-by: Ong Boon Leong <boon.leong....@intel.com> --- ...t-enable-board-file-for-BYT-LPSS-PCI-mode.patch | 156 ++++++++++++++++++++ 1 file changed, 156 insertions(+) create mode 100644 meta/cfg/kernel-cache/features/valleyisland-io/0014-x86-byt-enable-board-file-for-BYT-LPSS-PCI-mode.patch diff --git a/meta/cfg/kernel-cache/features/valleyisland-io/0014-x86-byt-enable-board-file-for-BYT-LPSS-PCI-mode.patch b/meta/cfg/kernel-cache/features/valleyisland-io/0014-x86-byt-enable-board-file-for-BYT-LPSS-PCI-mode.patch new file mode 100644 index 0000000..439999b --- /dev/null +++ b/meta/cfg/kernel-cache/features/valleyisland-io/0014-x86-byt-enable-board-file-for-BYT-LPSS-PCI-mode.patch @@ -0,0 +1,156 @@ +From bb940dfaa386364b2e8cee6a749dde8ebffe6453 Mon Sep 17 00:00:00 2001 +From: Chew, Chiau Ee <chiau.ee.c...@intel.com> +Date: Mon, 13 Jan 2014 00:43:59 +0800 +Subject: [PATCH 14/17] x86/byt: enable board file for BYT LPSS PCI mode + +This commit enables the following: +- setup clock tree for PCI mode SPI, DMA and PWM host + as the controller drivers require clock information during + device/driver probe +- register SPI slave + +Signed-off-by: Chew, Chiau Ee <chiau.ee.c...@intel.com> +Signed-off-by: Chang, Rebecca Swee Fun <rebecca.swee.fun.ch...@intel.com> +--- + arch/x86/Kconfig | 12 ++++ + arch/x86/platform/Makefile | 3 + arch/x86/platform/byt/Makefile | 1 + arch/x86/platform/byt/byt-board.c | 84 +++++++++++++++++++++++++++++++++++++ + 4 files changed, 99 insertions(+), 0 deletions(-) + create mode 100644 arch/x86/platform/byt/Makefile + create mode 100644 arch/x86/platform/byt/byt-board.c + +diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig +index 4067fc4..5bf0510 100644 +--- a/arch/x86/Kconfig ++++ b/arch/x86/Kconfig +@@ -467,6 +467,18 @@ config X86_INTEL_LPSS + things like clock tree (common clock framework) which are needed + by the LPSS peripheral drivers. + ++config BYT_LPSS_BRD ++ bool "PCI mode LPSS support on BYT" ++ depends on X86_INTEL_LPSS ++ ---help--- ++ If you choose yes, the platform board file enables ++ clock tree for PCI mode SPI, DMA and PWM host controllers. ++ In addition, the platform board provide device node for ++ SPI controller in order for user-space access. ++ ++ This option is needed if were to use Intel BayTrail LPSS in ++ PCI mode. ++ + config X86_RDC321X + bool "RDC R-321x SoC" + depends on X86_32 +diff --git a/arch/x86/platform/Makefile b/arch/x86/platform/Makefile +index 8d87439..e522a06 100644 +--- a/arch/x86/platform/Makefile ++++ b/arch/x86/platform/Makefile +@@ -9,3 +9,6 @@ obj-y += scx200/ + obj-y += sfi/ + obj-y += visws/ + obj-y += uv/ ++ifeq ($(CONFIG_BYT_LPSS_BRD),y) ++obj-y += byt/ ++endif +diff --git a/arch/x86/platform/byt/Makefile b/arch/x86/platform/byt/Makefile +new file mode 100644 +index 0000000..2d4af86 +--- /dev/null ++++ b/arch/x86/platform/byt/Makefile +@@ -0,0 +1 @@ ++obj-y += byt-board.o +diff --git a/arch/x86/platform/byt/byt-board.c b/arch/x86/platform/byt/byt-board.c +new file mode 100644 +index 0000000..be4ed4d +--- /dev/null ++++ b/arch/x86/platform/byt/byt-board.c +@@ -0,0 +1,84 @@ ++#include <linux/init.h> ++#include <linux/module.h> ++#include <linux/device.h> ++#include <linux/clk.h> ++#include <linux/clkdev.h> ++#include <linux/clk-provider.h> ++#include <linux/spi/spidev.h> ++#include <linux/spi/spi.h> ++#include <linux/spi/pxa2xx_spi.h> ++#include <linux/pwm.h> ++ ++static struct pxa2xx_spi_chip chip_data = { ++ .gpio_cs = -EINVAL, ++ .dma_burst_size = 32, ++}; ++ ++static struct spi_board_info byt_spi_slaves[] = { ++ { ++ .modalias = "spidev", ++ .max_speed_hz = 50000000, ++ .bus_num = 0, ++ .chip_select = 0, ++ .controller_data = &chip_data, ++ .mode = SPI_MODE_0, ++ } ++}; ++ ++static int byt_spi_board_setup(void) ++{ ++ int ret = -1; ++ ++ /* Register the SPI devices */ ++ if (!spi_register_board_info ++ (byt_spi_slaves, ARRAY_SIZE(byt_spi_slaves))) ++ ret = 0; ++ ++ return ret; ++} ++ ++static int byt_clk_setup(void) ++{ ++ struct clk *clk; ++ ++ /* Make clock tree required by the SPI/DMA/PWM driver */ ++ clk = clk_register_fixed_rate(NULL, "lpss_clk", NULL, CLK_IS_ROOT, ++ 100000000); ++ if (IS_ERR(clk)) ++ return PTR_ERR(clk); ++ ++ clk_register_clkdev(clk, "hclk", "dw_dmac.0"); ++ ++ clk = clk_register_fixed_rate(NULL, "spi_clk", "lpss_clk", 0, 50000000); ++ if (IS_ERR(clk)) ++ return PTR_ERR(clk); ++ ++ clk_register_clkdev(clk, NULL, "0000:00:1e.5"); ++ ++ clk = clk_register_fixed_rate(NULL, "pwm_clk", "lpss_clk", 0, 25000000); ++ if (IS_ERR(clk)) ++ return PTR_ERR(clk); ++ ++ clk_register_clkdev(clk, NULL, "0000:00:1e.1"); ++ clk_register_clkdev(clk, NULL, "0000:00:1e.2"); ++ ++ return 0; ++} ++ ++static int __init byt_board_init(void) ++{ ++ int ret; ++ ++ ret = byt_clk_setup(); ++ if (ret) ++ goto exit; ++ ++ ret = byt_spi_board_setup(); ++ if (ret) ++ goto exit; ++ ++exit: ++ return ret; ++} ++arch_initcall(byt_board_init); ++MODULE_LICENSE(GPL); +-- +1.7.4.4 + -- 1.7.10.4 _______________________________________________ linux-yocto mailing list linux-yocto@yoctoproject.org https://lists.yoctoproject.org/listinfo/linux-yocto