From: John Jacques <john.jacq...@lsi.com> Updated to work on 3500 emulation now that 3500 emulation is available.
Signed-off-by: John Jacques <john.jacq...@lsi.com> --- arch/powerpc/boot/dts/acp35xx.dts | 489 +++++++++++++++++++++++--------------- 1 file changed, 293 insertions(+), 196 deletions(-) diff --git a/arch/powerpc/boot/dts/acp35xx.dts b/arch/powerpc/boot/dts/acp35xx.dts index 4db67df..83a4c90 100644 --- a/arch/powerpc/boot/dts/acp35xx.dts +++ b/arch/powerpc/boot/dts/acp35xx.dts @@ -1,10 +1,10 @@ /* - * Device Tree Source for IBM Embedded PPC 476 Platform + * Device Tree Source for LSI ACP35xx. * - * Copyright 2009 Torez Smith, IBM Corporation. + * Copyright 2013, LSI Corporation * * Based on earlier code: - * Copyright (c) 2006, 2007 IBM Corp. + * Copyright (c) 2009, 2006, 2007 IBM Corp. * Josh Boyer <jwbo...@linux.vnet.ibm.com>, David Gibson <d...@au1.ibm.com> * * This file is licensed under the terms of the GNU General Public @@ -17,167 +17,279 @@ /memreserve/ 0x00000000 0x00400000; / { - #address-cells = <2>; - #size-cells = <1>; - model = "ibm,acpx1-4xx"; - compatible = "ibm,acpx1-4xx","ibm,47x-AMP"; - dcr-parent = <&{/cpus/cpu@0}>; - - aliases { - serial0 = &UART0; - serial1 = &UART1; - rapidio0 = &rio0; + #address-cells = <2>; + #size-cells = <1>; + model = "ibm,acpx1-4xx"; + compatible = "ibm,acpx1-4xx","ibm,47x-AMP"; + dcr-parent = <&{/cpus/cpu@0}>; + + aliases { + serial0 = &UART0; + serial1 = &UART1; ethernet0 = &FEMAC; - }; + rapidio0 = &SRIO0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + model = "PowerPC,4xx"; // real CPU changed in sim + reg = <0>; + clock-frequency = <0x5f5e1000>; // filled in by U-Boot + timebase-frequency = <0x5f5e1000>; // filled in by U-Boot + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; + dcr-controller; + dcr-access-method = "native"; + status = "ok"; + reset-type = <3>; // 1=core, 2=chip, 3=system (default) + }; + + cpu@1 { + device_type = "cpu"; + model = "PowerPC,4xx"; // real CPU changed in sim + reg = <1>; + clock-frequency = <0x5f5e1000>; // filled in by U-Boot + timebase-frequency = <0x5f5e1000>; // filled in by U-Boot + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; + dcr-controller; + dcr-access-method = "native"; + status = "disabled"; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; // Fixed by the boot loader + reset-type = <3>; // 1=core, 2=chip, 3=system (default) + }; + + cpu@2 { + device_type = "cpu"; + model = "PowerPC,4xx"; // real CPU changed in sim + reg = <2>; + clock-frequency = <0x5f5e1000>; // filled in by U-Boot + timebase-frequency = <0x5f5e1000>; // filled in by U-Boot + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; + dcr-controller; + dcr-access-method = "native"; + status = "disabled"; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; // Fixed by the boot loader + reset-type = <3>; // 1=core, 2=chip, 3=system (default) + }; + + + cpu@3 { + device_type = "cpu"; + model = "PowerPC,4xx"; // real CPU changed in sim + reg = <3>; + clock-frequency = <0x5f5e1000>; // filled in by U-Boot + timebase-frequency = <0x5f5e1000>; // filled in by U-Boot + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; + dcr-controller; + dcr-access-method = "native"; + status = "disabled"; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; // Fixed by the boot loader + reset-type = <3>; // 1=core, 2=chip, 3=system (default) + }; + + cpu@4 { + device_type = "cpu"; + model = "PowerPC,4xx"; // real CPU changed in sim + reg = <4>; + clock-frequency = <0x5f5e1000>; // filled in by U-Boot + timebase-frequency = <0x5f5e1000>; // filled in by U-Boot + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; + dcr-controller; + dcr-access-method = "native"; + status = "disabled"; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; // Fixed by the boot loader + reset-type = <3>; // 1=core, 2=chip, 3=system (default) + }; + + cpu@5 { + device_type = "cpu"; + model = "PowerPC,4xx"; // real CPU changed in sim + reg = <5>; + clock-frequency = <0x5f5e1000>; // filled in by U-Boot + timebase-frequency = <0x5f5e1000>; // filled in by U-Boot + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; + dcr-controller; + dcr-access-method = "native"; + status = "disabled"; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; // Fixed by the boot loader + reset-type = <3>; // 1=core, 2=chip, 3=system (default) + }; - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - model = "PowerPC,4xx"; // real CPU changed in sim - reg = <0>; - clock-frequency = <0x5f5e1000>; - timebase-frequency = <0x5f5e1000>; - i-cache-line-size = <32>; - d-cache-line-size = <32>; - i-cache-size = <32768>; - d-cache-size = <32768>; - dcr-controller; - dcr-access-method = "native"; - status = "ok"; - reset-type = <3>; // 1=core, 2=chip, 3=system (default) - }; - }; + + + }; memory@0 { device_type = "memory"; - reg = <0x00000000 0x00000000 0x80000000>; // filled in by U-Boot + reg = <0x00000000 0x00000000 0x08000000>; // filled in by U-Boot }; memory@80000000 { device_type = "memory"; - reg = <0x00000000 0x80000000 0x80000000>; // filled in by U-Boot + reg = <0x00000000 0x08000000 0x08000000>; // filled in by U-Boot }; - MPIC: interrupt-controller { - compatible = "chrp,open-pic"; - interrupt-controller; - dcr-reg = <0xffc00000 0x00030000>; - #address-cells = <0>; - #size-cells = <0>; - #interrupt-cells = <2>; - pic-no-reset; - }; + MPIC: interrupt-controller { + compatible = "chrp,open-pic"; + interrupt-controller; + dcr-reg = <0xffc00000 0x00030000>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + pic-no-reset; + }; - plb { - /* Could be PLB6, doesn't matter */ - compatible = "ibm,plb-4xx", "ibm,plb4"; - #address-cells = <2>; - #size-cells = <1>; - ranges; - clock-frequency = <0>; // Filled in by zImage - - POB0: opb { - compatible = "ibm,opb-4xx", "ibm,opb"; - #address-cells = <1>; - #size-cells = <1>; - /* Wish there was a nicer way of specifying a full 32-bit - range */ - ranges = <0x00000000 0x00000020 0x00000000 0x80000000 - 0x80000000 0x00000020 0x80000000 0x80000000>; - clock-frequency = <0>; // Filled in by zImage - UART0: serial@00404000 { - device_type = "serial"; - compatible = "acp-uart0"; - enabled = <1>; - reg = <0x00404000 0x1000>; - clock-reg = <0x00408040 0x20>; - clock-frequency = <0xbebc200>; - current-speed = <9600>; - interrupt-parent = <&MPIC>; - interrupts = <22>; - }; - UART1: serial@00405000 { - device_type = "serial"; - compatible = "acp-uart1"; - enabled = <0>; - reg = <0x00405000 0x1000>; - clock-reg = <0x00408060 0x20>; - clock-frequency = <200000000>; - current-speed = <9600>; - interrupt-parent = <&MPIC>; - interrupts = <23>; - }; - USB0: usb@004a4000 { - device_type = "usb"; - compatible = "acp-usb"; - enabled = <0>; - reg = <0x004a4000 0x00020000>; - interrupt-parent = <&MPIC>; - interrupts = <31>; - }; - I2C: i2c@00403000 { - compatible = "acp-i2c"; - enabled = <0>; - reg = <0x00403000 0x00001000>; - interrupt-parent = <&MPIC>; - interrupts = <21>; - }; - SSP: ssp@00402000 { - compatible = "acp-ssp"; - enabled = <0>; - reg = <0x00402000 0x00001000>; - interrupt-parent = <&MPIC>; - interrupts = <20>; - }; - NAND: nand@00440000 { - device_type = "nand"; - compatible = "acp-nand"; - enabled = <1>; - reg = <0x00440000 0x20000 - 0x0040c000 0x1000>; - }; - FEMAC: femac@00480000 { - device_type = "network"; - compatible = "acp-femac"; - enabled = <1>; - reg = <0x00480000 0x1000 - 0x00481000 0x1000 - 0x00482000 0x1000>; - interrupt-parent = <&MPIC>; - interrupts = <33>; - mdio-reg = <0x00409000 0x1000>; - // The following will get filled in by - // the boot loader. - mdio-clock = <0>; - phy-address = <0>; - ad-value = <0>; - mac-address = [00 00 00 00 00 00]; - }; - }; - }; + plb { + /* Could be PLB6, doesn't matter */ + compatible = "ibm,plb-4xx", "ibm,plb4"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + clock-frequency = <0>; // Filled in by zImage + POB0: opb { + compatible = "ibm,opb-4xx", "ibm,opb"; + #address-cells = <1>; + #size-cells = <1>; + /* Wish there was a nicer way of specifying a full 32-bit + range */ + ranges = <0x00000000 0x00000020 0x00000000 0x80000000 + 0x80000000 0x00000020 0x80000000 0x80000000>; + clock-frequency = <0>; // Filled in by zImage - nvrtc { - compatible = "ds1743-nvram", "ds1743", "rtc-ds1743"; - reg = <0 0xEF703000 0x2000>; - }; + UART0: serial0 { + device_type = "serial"; + compatible = "acp-uart0"; + enabled = <0>; + reg = <0x00424000 0x1000>; + clock-reg = <0x00429040 0x20>; + clock-frequency = <200000000>; + current-speed = <9600>; + interrupt-parent = <&MPIC>; + interrupts = <29>; + /*interrupts = <23>;*/ + }; - system { - ncr_0x00a_0x010_0x0002c = <0>; // filled in by the boot loader. - ncr_0x016_0x0ff_0x00010 = <0>; // filled in by the boot loader. - }; + UART1: serial1 { + device_type = "serial"; + compatible = "acp-uart1"; + enabled = <0>; + reg = <0x00425000 0x1000>; + clock-reg = <0x00429060 0x20>; + clock-frequency = <200000000>; + current-speed = <9600>; + interrupt-parent = <&MPIC>; + interrupts = <30>; + }; - chosen { - linux,stdout-path = "/plb/opb/serial@00404000"; - }; + USB0: usb0 { + device_type = "usb"; + compatible = "acp-usb"; + enabled = <0>; + reg = <0x004a4000 0x00020000>; + interrupt-parent = <&MPIC>; + interrupts = <36>; + }; + + I2C: i2c0 { + compatible = "acp-i2c"; + enabled = <0>; + reg = <0x00403000 0x00001000>; + interrupt-parent = <&MPIC>; + interrupts = <27>; + }; + + SSP: ssp0 { + compatible = "acp-ssp"; + enabled = <0>; + reg = <0x00402000 0x00001000>; + interrupt-parent = <&MPIC>; + interrupts = <26>; + }; + + NAND: nand0 { + device_type = "nand"; + compatible = "acp-nand"; + enabled = <0>; + reg = <0x004e0000 0x20000 + 0x00400000 0x1000>; + }; - PCIE0: pciex@f00c0000 { + FEMAC: femac0 { + device_type = "network"; + compatible = "acp-femac"; + enabled = <0>; + reg = <0x00480000 0x1000 + 0x00481000 0x1000 + 0x00482000 0x1000>; + interrupt-parent = <&MPIC>; + interrupts = <38>; + /*interrupts = <32>;*/ + mdio-reg = <0x0042a000 0x1000>; + // The following will get filled in by + // the boot loader. + mdio-clock = <0>; + phy-address = <0>; + ad-value = <0>; + mac-address = [00 00 00 00 00 00]; + }; + + SBB: sbb0 { + name = "sbb0"; + enabled = <0>; + ecm-dcr = <0x1300>; + sbb-reg = <0x00500000 0x8000>; + tzc-reg = <0x00541000 0x1000>; + }; + }; + }; + + + nvrtc { + compatible = "ds1743-nvram", "ds1743", "rtc-ds1743"; + reg = <0 0xEF703000 0x2000>; + }; + + system { + ncr_0x00a_0x010_0x0002c = <0>; // filled in by the boot loader. + ncr_0x016_0x0ff_0x00010 = <0>; // filled in by the boot loader. + }; + + chosen { + bootargs = "console=ttyS0 ip=dhcp root=/dev/nfs rw"; + linux,stdout-path = "/plb/opb/serial0"; + }; + + PCIE0: pei0 { compatible = "lsi,plb-pciex"; device_type = "pci"; - enabled = <0>; + enabled = <0x0>; plx = <0>; primary; port = <0>; @@ -185,8 +297,8 @@ #size-cells = <2>; #address-cells = <3>; /* config space access MPAGE7 registers*/ - reg = < 0x0020 0x78000000 0x01000000 - 0x0020 0x004c0000 0x00008000 >; + reg = <0x0020 0x78000000 0x01000000 + 0x0020 0x00580000 0x00008000>; bus-range = <0 0x0f>; /* Outbound ranges */ /* < <3-cell PCI addr> <2-cell CPU (PLB) addr> <2-cell size> > */ @@ -199,18 +311,18 @@ 0x00 0x00000000 0x00 0x10000000>; interrupt-parent = <&MPIC>; - interrupts = <29 2>; + interrupts = <52 2>; interrupt-map-mask = <0000 0 0 7>; interrupt-map = < /* <3-cell dev> <irq#> <prnt> <2-cell prnt IRQ/sense> */ - 0000 0 0 1 &MPIC 29 2 - 0000 0 0 2 &MPIC 29 2 - 0000 0 0 3 &MPIC 29 2 - 0000 0 0 4 &MPIC 29 2 + 0000 0 0 1 &MPIC 52 2 + 0000 0 0 2 &MPIC 52 2 + 0000 0 0 3 &MPIC 52 2 + 0000 0 0 4 &MPIC 52 2 >; }; - PCIE1: pciex@f00c8000 { + PCIE1: pei1 { compatible = "lsi,plb-pciex"; device_type = "pci"; enabled = <0>; @@ -221,13 +333,13 @@ #size-cells = <2>; #address-cells = <3>; /* config space access MPAGE7 registers*/ - reg = <0x0020 0xf8000000 0x01000000 - 0x0020 0x004c8000 0x00008000 >; + reg = <0x0020 0xb8000000 0x01000000 + 0x0020 0x00588000 0x00008000>; bus-range = <0 0x0f>; /* Outbound ranges */ /* < <3-cell PCI addr> <2-cell CPU (PLB) addr> <2-cell size> > */ - ranges = <0x02000000 0x00000000 0xa0000000 - 0x20 0xc0000000 + ranges = <0x02000000 0x00000000 0xb0000000 + 0x20 0x80000000 0x00 0x10000000>; /* Inbound ranges */ /* < <3-cell PCI addr> <2-cell CPU addr> <2-cell size> > */ @@ -235,18 +347,17 @@ 0x00 0x00000000 0x00 0x10000000>; interrupt-parent = <&MPIC>; - interrupts = <72 2>; + interrupts = <54 2>; interrupt-map-mask = <0000 0 0 7>; interrupt-map = < /* <3-cell dev> <irq#> <prnt> <2-cell prnt IRQ/sense> */ - 0000 0 0 1 &MPIC 72 2 - 0000 0 0 2 &MPIC 72 2 - 0000 0 0 3 &MPIC 72 2 - 0000 0 0 4 &MPIC 72 2 + 0000 0 0 1 &MPIC 54 2 + 0000 0 0 2 &MPIC 54 2 + 0000 0 0 3 &MPIC 54 2 + 0000 0 0 4 &MPIC 54 2 >; }; - - PCIE2: pciex@f00d0000 { + PCIE2: pei2 { compatible = "lsi,plb-pciex"; device_type = "pci"; enabled = <0>; @@ -257,13 +368,13 @@ #size-cells = <2>; #address-cells = <3>; /* config space access MPAGE7 registers*/ - reg = <0x0021 0x38000000 0x01000000 - 0x0020 0x004d0000 0x00008000 >; + reg = <0x0020 0xf8000000 0x01000000 + 0x0020 0x00590000 0x00008000>; bus-range = <0 0x0f>; /* Outbound ranges */ /* < <3-cell PCI addr> <2-cell CPU (PLB) addr> <2-cell size> > */ - ranges = <0x02000000 0x00000000 0xa0000000 - 0x21 0x00000000 + ranges = <0x02000000 0x00000000 0xc0000000 + 0x20 0xc0000000 0x00 0x10000000>; /* Inbound ranges */ /* < <3-cell PCI addr> <2-cell CPU addr> <2-cell size> > */ @@ -272,38 +383,24 @@ 0x00 0x10000000>; interrupt-parent = <&MPIC>; - interrupts = <73 2>; + interrupts = <55 2>; interrupt-map-mask = <0000 0 0 7>; interrupt-map = < /* <3-cell dev> <irq#> <prnt> <2-cell prnt IRQ/sense> */ - 0000 0 0 1 &MPIC 73 2 - 0000 0 0 2 &MPIC 73 2 - 0000 0 0 3 &MPIC 73 2 - 0000 0 0 4 &MPIC 73 2 + 0000 0 0 1 &MPIC 55 2 + 0000 0 0 2 &MPIC 55 2 + 0000 0 0 3 &MPIC 55 2 + 0000 0 0 4 &MPIC 55 2 >; }; - - rio0: rapidio@f0020000 { - compatible = "acp,rapidio-delta"; ++ SRIO0: srio0 { ++ compatible = "acp,rapidio-delta"; device_type = "rapidio"; - enabled = <0>; - #size = <0>; /* 0 = (256, small system) - * 1 = (65536, large system) */ -/* - #host-device-id = <1>; -*/ - /* >=0 for enum; < 0 for disc */ -/* - num-dme = <1 0 1>; -*/ - /* (#outb-mseg>, <#outb-sseg>, <#inb> */ -/* - num-odme-mseg-desc = <2 128 128>; - num-odme-sseg-desc = <1 256>; - num-idme-desc = <1 512>; -*/ - reg = <0xf0020000 0x20000 0x1000>; /* SRIO Conf region */ - interrupt-parent = <&MPIC>; - interrupts = <30 0x2 /* NCP_INTR_MPIC_SRC_AXIS_SRIO */>; - }; + enabled = <0>; + #size = <0>; /* 0 = (256, small system) + * 1 = (65536, large system) */ + reg = <0xf0020000 0x20000 0x1000>; /* SRIO Conf region */ + interrupt-parent = <&MPIC>; + interrupts = <56 0x2 /* NCP_INTR_MPIC_SRC_AXIS_SRIO */>; + }; }; -- 1.8.4.3 _______________________________________________ linux-yocto mailing list linux-yocto@yoctoproject.org https://lists.yoctoproject.org/listinfo/linux-yocto