Hello,
I have been communicating with the Linuxbios mailing list on and off
(mostly off lately). I'm interested to try out the linuxBIOS on my old
dual CPU board MSI-6120. The current MSI/AMI BIOS V2.0 does not support
newer CPUs than Coppermine.
Currently I have two old PII processors
--- Svante Signell [EMAIL PROTECTED] wrote:
dual CPU board MSI-6120. The current MSI/AMI BIOS
V2.0 does not support
newer CPUs than Coppermine.
Porting 440bx to V2 is on my TODO list but it's
currently blocked by a few other priorities.
The V1 code should work for you fine. All you need
I need to start looking at moving the 440bx stuff to
V2. The part I'm most concerned about is re-writing
the ram init code.
Is it possible to use the V2 structure but graft in
the assembly output from V1? Then as time permits I
can go back and re-write those routines.
Tell me again which is
On Tue, 11 Jan 2005, Adam Talbot wrote:
-LinuxBios Guy's OK, well if Intel won't play nice then i will have to
see what i can do by back tracking a stock 855GME bios... Do-able, but a
pain. I am going to try to get linuxbios installed on a LV-671
motherboard... I will keep you guy's
On Wed, 12 Jan 2005, Gin wrote:
The system failed when booting SMP linux kernel. It complains the IDE
lost interrupt. Things were working fine with the non-SMP linux kernel.
Has anyone seen it before?
bad mp table would be my guess.
ron
___
On Tue, 11 Jan 2005, Adam Talbot wrote:
Need some way to test if linuxbios is booting correctly. I am debugging and
I have reason to believe that my problem is the super io... Does any one
know how to get the pc speaker to beep in X second intervals, or some thing
that simple, power LED
On Wed, Jan 12, 2005 at 10:38:57AM +0100, Svante Signell wrote:
Where can I purchase a replacement BIOS chip? Placed in a socket on
the main board is a 2x16 pin DIL labeled: 686 AMI BIOS 1995 CS
9.
Please remove the shiny sticker and check how the actual package is
marked. You're looking
Richard Smith [EMAIL PROTECTED] writes:
I need to start looking at moving the 440bx stuff to
V2. The part I'm most concerned about is re-writing
the ram init code.
Is it possible to use the V2 structure but graft in
the assembly output from V1? Then as time permits I
can go back and
--- Eric W. Biederman ebiederman@lnxi.com wrote:
Something like the via epia, q-emu should be ok. I
don't really
know as I have not looked at the simple embedded
case lately. In the
last round of cleanups I'm pretty certain we managed
to purge the
worst of the bad examples from the tree
On Wed, 12 Jan 2005, Richard Smith wrote:
Is it possible to use the V2 structure but graft in
the assembly output from V1? Then as time permits I
can go back and re-write those routines.
bite the bullet. Just write the C. I've tried both ways and the C is just
plain easier.
I would go
Adam Talbot [EMAIL PROTECTED] writes:
Need some way to test if linuxbios is booting correctly. I am debugging and
I have reason to believe that my problem is the super io... Does any one
know how to get the pc speaker to beep in X second intervals, or some thing
that simple, power LED
On Wed, 12 Jan 2005, Richard Smith wrote:
IIRC the q-emu wasn't really complete enough for my
purposes. I'll start with epia and go from there.
sorry, richard, I misunderstood your question. Yeah, try the epia.
ron
___
Linuxbios mailing list
--- Ronald G. Minnich rminnich@lanl.gov wrote:
bite the bullet. Just write the C. I've tried both
ways and the C is just
plain easier.
The problem with that is that it requires me to
actually go _understand_ the code. *grin* I fixed a
few bugs in the origial asm code but most of it
On Wed, 12 Jan 2005, Eric W. Biederman wrote:
Unfortunately I don't believe we have an pc-speaker output coded for the
LinuxBIOS case. I keep play with the idea of morse code console, using
the pc-speaker :) You would not want full debugging on but it might be
useful for your kind of
On Wed, 12 Jan 2005, Richard Smith wrote:
Dose either this one or the epia read the SPD eproms
and set the registers accordingly?
you mean does the EPIA read the SPD? Yes it does, and
somebody recently fixed a bunch of bugs so it does a better job that it
used to.
ron
Eric W. Biederman wrote:
I think morse code would actually tie in better with the post code
infrastructure than general console traffic. That would keep
the volume of data low enough so as to be meaningful. Even
if you did not know morse code.
Then maybe you could use one of these instead of a
A morse code decoder for decoding Audio console. Wow, our geek is
hanging out! :-) if some one have that much spair time... But for now, one
or two simple beeps would make me VERY happy.
As far a POST card, I do not have one... Yet. What POST card have your guys
had good luck with (PCI)?
-Adam
Cool!
-Original Message-
From: Bari Ari [mailto:[EMAIL PROTECTED]
Sent: Wednesday, January 12, 2005 10:44 AM
To: Eric W. Biederman
Cc: Ronald G. Minnich; Adam Talbot; Linuxbios@clustermatic.org
Subject: Re: speaker beeper
Eric W. Biederman wrote:
I think morse code would actually tie
On Wed, 12 Jan 2005, Adam Talbot wrote:
As far a POST card, I do not have one... Yet. What POST card have your guys
had good luck with (PCI)?
For 5V PCI bus the company I used to buy from no longer sells it, oops (I
just checked)
anybody?
ron
If you compilie in llshell, it will beep the speaker whenever called
(this can be at any stage).
Also, type beep at the command prompt, assuming you have serial.
(2nd try, apologies if you get this twice)
___
Linuxbios mailing list
* Bari Ari [EMAIL PROTECTED] [050112 19:43]:
Eric W. Biederman wrote:
I think morse code would actually tie in better with the post code
infrastructure than general console traffic. That would keep
the volume of data low enough so as to be meaningful. Even
if you did not know morse
I don't understand the cpu naming scheme in the
cpu/intel dirctory.
Our board uses a PIII Celeron in a PGA socket 370 @
400 Mhz
should I just call the directory socket_PGA370 or do I
need to add speed info? What about the Celeron,
non-celeron difference?
=
Richard A. Smith
Bitworks, Inc.
On Wed, 2005-01-12 at 17:23, YhLu wrote:
Please check the update S2850, and it support onboard ATI via
emulator.
How is the emulator been called?
Ollie
For command line? FILO,? Please refer Etherboot/src/filo/*.txt
Regards
YH
I add driver/pci/onboard, it will take rom_address in conf.
Also add some line in pci_rom.c
/* for the onboard vga it already got one VGA rom space ? bug
it should be allocated and just use the assigned value
*/
if(dev-on_mainboard) {
The chip.h is already in /drivers/pci/onboard.
So may need to
#include ../drivers/pci/onboard/chip.h
In pci_device.c
Also in get_pci_rom_resource begin
Add
if(dev-on_mainboard) {
struct drivers_pci_onboard_config *conf;
conf = dev-chip_info;
On Wed, 2005-01-12 at 18:59, YhLu wrote:
The chip.h is already in /drivers/pci/onboard.
So may need to
#include ../drivers/pci/onboard/chip.h
In pci_device.c
How about we bring the device:rom_address back and in the
driver_pci_onboard::enable_dev(dev)
{
dev-rom_address =
much better,
Because don't need to cast conf to drivers_pci_onboard_config, it is not
safe in pci_rom.c or pci_device.c
Do it.
YH
How about we bring the device:rom_address back and in the
driver_pci_onboard::enable_dev(dev)
{
dev-rom_address = conf-rom_address;
}
and in
bad mp table would be my guess.
I think the I/O APICs are incorrectly assigned to buses. From the kernel
messages, devices on bus 0 are transformed to high IRQs.
Can anyone one confirm that the mptable.c under src/tyan/s2735 is a good
one to boot SMP linux kernel? I might need to manually
Check put this post card. What do you think.
http://www.compgeeks.com/details.asp?invtid=SY-TECHAID
http://www.soyogroup.com/dl/manuals/peripherals/techaid_manual_v10.pdf
-Adam
- Original Message -
From: Ronald G. Minnich rminnich@lanl.gov
To: Adam Talbot [EMAIL PROTECTED]
Cc: Bari Ari
Adam Talbot wrote:
Check put this post card. What do you think.
http://www.compgeeks.com/details.asp?invtid=SY-TECHAID
http://www.soyogroup.com/dl/manuals/peripherals/techaid_manual_v10.pdf
-Adam
For only $28.75 it looks great.
-Bari
___
Linuxbios
Richard Smith [EMAIL PROTECTED] writes:
I don't understand the cpu naming scheme in the
cpu/intel dirctory.
Our board uses a PIII Celeron in a PGA socket 370 @
400 Mhz
should I just call the directory socket_PGA370 or do I
need to add speed info? What about the Celeron,
non-celeron
Committed.
Also I added readme in /drivers/pci/onboard/onboard.c
YH
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Linuxbios@clustermatic.org
http://www.clustermatic.org/mailman/listinfo/linuxbios
-Eric
Console... Well running is a big word :-). I get garbage to the screen,
so I no that some of Linux bios is loading. I know that the console
connection is good, added console support to GRUB, that works great.
Currently I am looking over
freebios2/src/northbridge/intel/i855pm/raminit.c.
You assign the value to the new resource.
I wonder if it will confuse the resource allocator. Because the range is out
of touch of allocator.
YH
-Original Message-
From: Li-Ta Lo [mailto:[EMAIL PROTECTED]
Sent: Wednesday, January 12, 2005 9:48 PM
To: YhLu
Cc: Sagiv Yefet; LinuxBIOS
I used the phoenix bios to boot up and then dumped out
the northbridge. Then I called dumpnorth at
ram_setup_end, which is prior to Copying LinuxBIOS to
ram. The diff of the two was as below:
linux:
40: 1e 12 00 c1 00 00 00 00 00 00 00 00 00 00 00 00
---
phoenix:
40: 00 10 00 47 00 00 00 00 00
On Wed, 2005-01-12 at 23:07, YhLu wrote:
You assign the value to the new resource.
I wonder if it will confuse the resource allocator. Because the range is out
of touch of allocator.
I don't think so but I am not sure neither. The resource is flagged as
FIXED and ASSIGNED. The resource
hi richard,
yup, sounds pretty much like it. mine's a gx1/cs5530a
combo. i just posted about my latest status. i'm
starting to suspect that the ram setup might be fine.
it could be that i might have somehow misconfigured my
linuxbios build. i had sent an email where i detailed
what i think is
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