] AMD-8111 LPC (rev 5).
-邮件原件-
发件人: Stefan Reinauer [mailto:[EMAIL PROTECTED]
发送时间: 2003年9月11日 5:05
收件人: ron minnich
抄送: YhLu; [EMAIL PROTECTED]; LinuxBIOS
主题: Re: [COMMIT] Infrastructure Updates 4
* ron minnich <[EMAIL PROTECTED]> [030908 17:03]:
> On Mon, 8 Sep 2003, Stefan
Stefan Reinauer <[EMAIL PROTECTED]> writes:
> * Eric W. Biederman <[EMAIL PROTECTED]> [030908 22:04]:
> > Stefan Reinauer <[EMAIL PROTECTED]> writes:
> >
> > > uses XIP_ROM_SIZE
> > > uses XIP_ROM_BASE
> > > [..]
> > > option CONFIG_CHIP_CONFIGURE=1
> > > option CPU_FIXUP=1
> > > option CONFIG_UD
On Thu, 11 Sep 2003, Stefan Reinauer wrote:
> > Correct. It is a little better on the HDAMA. But currently there are
> > some options that don't seem to work properly when I move them in closer.
>
> The above was taken from the hdama CVS.
> So is there a difference for the build process whether
* Eric W. Biederman <[EMAIL PROTECTED]> [030908 22:04]:
> Stefan Reinauer <[EMAIL PROTECTED]> writes:
>
> > uses XIP_ROM_SIZE
> > uses XIP_ROM_BASE
> > [..]
> > option CONFIG_CHIP_CONFIGURE=1
> > option CPU_FIXUP=1
> > option CONFIG_UDELAY_TSC=0
> > option i686=1
> > option i586=1
> > option INTEL
* ron minnich <[EMAIL PROTECTED]> [030908 17:03]:
> On Mon, 8 Sep 2003, Stefan Reinauer wrote:
>
> > Did you have a look at the implementation of hard_reset in reset.c?
> > void hard_reset(void)
> > {
> > set_bios_reset();
> > pci_write_config8(PCI_DEV(1, 0x04, 0), 0x47, 1);
> > }
For the s2880/2882/2885, Amd8111 LPC is actually the PCI_DEV(1,0x4,0).
Regards
Yinghai Lu
-邮件原件-
发件人: ron minnich [mailto:[EMAIL PROTECTED]
发送时间: 2003年9月8日 8:03
收件人: Stefan Reinauer
抄送: YhLu; [EMAIL PROTECTED]; LinuxBIOS
主题: Re: [COMMIT] Infrastructure Updates 4
On Mon, 8 Sep 2003
YhLu <[EMAIL PROTECTED]> writes:
> Eric,
>
> In the k8/cpufixup.c, you have use 0x3f for TOM ( you said leave 64M for
> ROM and Device IO). In case that if the device need more MMIO range, it will
> produce problems for example AGP. So You need compare mmio_basek with
> 0x3f to see if mmi
On 8 Sep 2003, Eric W. Biederman wrote:
> Correct. It is a little better on the HDAMA. But currently there are
> some options that don't seem to work properly when I move them in closer.
yes, I've seen this too, not had time to fix it. Clearly, some things
should move into the mainboard file.
Stefan Reinauer <[EMAIL PROTECTED]> writes:
> * ron minnich <[EMAIL PROTECTED]> [030904 17:49]:
> > On Thu, 4 Sep 2003, Stefan Reinauer wrote:
> >
> > > I agree.. but right now there are still Config.lb files in the mainboard
> > > and in the targets directory. And at least last time I checked bo
YhLu <[EMAIL PROTECTED]> writes:
> Eric,
>
> Without hard_reset, s2885 is ok now.
>
> In the k8/cpufixup.c need compare mmio_basek and 0x3f and then assign
> that to TOM.
Hmm. What is special about 0x3f?
In any event this sounds promising. It looks like the reset needs to move
a littl
Any inconsistencies you find in the options are most certainly real. :-)
Much of the confusion comes from the configuration setup in the old
tree which allowed options to be specified and set in any config
file. The result was that many options were duplicated because their
definition was burie
On Mon, 8 Sep 2003, Stefan Reinauer wrote:
> * YhLu <[EMAIL PROTECTED]> [030906 04:58]:
> > Eric,
> >
> > Without hard_reset, s2885 is ok now.
>
> Did you have a look at the implementation of hard_reset in reset.c?
> void hard_reset(void)
> {
> set_bios_reset();
> pci_write_conf
* YhLu <[EMAIL PROTECTED]> [030906 04:58]:
> Eric,
>
> Without hard_reset, s2885 is ok now.
Did you have a look at the implementation of hard_reset in reset.c?
void hard_reset(void)
{
set_bios_reset();
pci_write_config8(PCI_DEV(1, 0x04, 0), 0x47, 1);
}
It looks like if the bus n
* ron minnich <[EMAIL PROTECTED]> [030904 17:49]:
> On Thu, 4 Sep 2003, Stefan Reinauer wrote:
>
> > I agree.. but right now there are still Config.lb files in the mainboard
> > and in the targets directory. And at least last time I checked both were
> > used.
>
> possibly I am missing your point
Eric,
Without hard_reset, s2885 is ok now.
In the k8/cpufixup.c need compare mmio_basek and 0x3f and then assign
that to TOM.
Regards
YH
-邮件原件-
发件人: YhLu
发送时间: 2003年9月4日 12:44
收件人: [EMAIL PROTECTED]
抄送: Stefan Reinauer; LinuxBIOS
主题: Re: [COMMIT] Infrastructure Updates 4
Eric
Eric,
The AGP display Adapter shown out too.
When enumerating the CPU 0 Link0 for 8151, it first collapse the early
non-conherent device 5:0.0 ( 8151) and then assign unit id (1) to him. So
the device id is change to 5:1.0. After that on bus5 there is a invalid
device 5:0.0 is there.( Child of B
ons
PCI: 05:01.0 [1022/7454] ops
PCI: 05:01.0 [1022/7454] enabled
PCI: 05:02.0 [1022/7455] bus ops
PCI: 05:02.0 [1022/7455] enabled
Copying LinuxBIOS to ram.
-邮件原件-
发件人: YhLu
发送时间: 2003年9月4日 10:48
收件人: [EMAIL PROTECTED]
抄送: Stefan Reinauer; LinuxBIOS
主题: re: [COMMIT] Infrastructure Update
10:30
收件人: '[EMAIL PROTECTED]'
抄送: Stefan Reinauer; LinuxBIOS
主题: Re: [COMMIT] Infrastructure Updates 4
I still have problems for s2885.
Amdk8_scan_bus for MC0 only from link0 to link2. link0 is connected to 8151
and link2 is connected to 8131.
Then it reboot again and agin.
After I r
--邮件原件-
发件人: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]
发送时间: 2003年9月3日 20:09
收件人: YhLu
抄送: Stefan Reinauer; LinuxBIOS
主题: Re: [COMMIT] Infrastructure Updates 4
YhLu <[EMAIL PROTECTED]> writes:
> Eric,
>
> Please check function hypertransport_scan_chain definition and calling
On Thu, 4 Sep 2003, Stefan Reinauer wrote:
> I agree.. but right now there are still Config.lb files in the mainboard
> and in the targets directory. And at least last time I checked both were
> used.
possibly I am missing your point. What bits did you want to see in
mainboard/Config.lb that are
* ron minnich <[EMAIL PROTECTED]> [030904 16:22]:
> One of the goals of the new tool was to bring everything up to the top
> level. People were getting lost in the maze of include files and option
> settings. The disadvantage, as you point out, is some duplicated code, but
> the advantages have
On 3 Sep 2003, Eric W. Biederman wrote:
> >
> > * the logical devices of the amd8131 pci-x bridge has to be described in
> > the mainboard configuration file. This means a lot of duplicate config
> > "code" spread over the mainboard directory. Can this somehow go to the
> > Config.lb file
On Wed, 3 Sep 2003, Stefan Reinauer wrote:
> > > Does it look like this? :
> > >
> > >8111
> > > |
> > >8131
> > > |
> > >CPU0 -- CPU1
> >
> > Yes. The order of the device structures is significant.
>
> should this:
>
> southbridge amd/amd8131 "amd8131"
>
On 3 Sep 2003, Eric W. Biederman wrote:
> > I started digging through the code, but I am not completely there yet.
> > It seems to me it would make sense to move the register "up" information
> > from cpu k8 "cpu0" to the northbridge amd/amdk8 "mc0" definition since
> > its information associated
YhLu <[EMAIL PROTECTED]> writes:
> Eric,
>
> Please check function hypertransport_scan_chain definition and calling
> parameters.
>
> It seems the .h and .c is not consistent.
You are right. I have removed the middle parameter (something I was playing with)
from northbridge.c and hypertranspor
Eric,
Please check function hypertransport_scan_chain definition and calling
parameters.
It seems the .h and .c is not consistent.
Regards
YH
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YhLu <[EMAIL PROTECTED]> writes:
> I have tried in s2880.
>
> southbridge amd/amd8131 "amd8131"
> pci 0:0.0
> pci 0:0.1
> pci 0:1.0
> pci 0:1.1
> southbridge amd/amd8111 "amd8111"
> pc
Stefan Reinauer <[EMAIL PROTECTED]> writes:
> * Eric W. Biederman <[EMAIL PROTECTED]> [030903 17:47]:
> > First the most basic result I have is that I need to know what all of the
> > logical devices that come out of a chip are.
>
> > So off of each logical device I have one or more channels. T
YhLu <[EMAIL PROTECTED]> writes:
> Eric,
>
> For s2885
>
> 8151
> | (link0)
> CPU0 -- CPU1
>| (link2)
> 8131
>|
> 8111
>
>
> So the Config.lb should include
With the current code the configuration should say:
northbridge amd/amdk8 "mc0"
pci
27;course, if LDTSTOP# or reset# is not asserted, the
regs has no meanings.
YH
-邮件原件-
发件人: Stefan Reinauer [mailto:[EMAIL PROTECTED]
发送时间: 2003年9月3日 9:13
收件人: Eric W. Biederman
抄送: LinuxBIOS
主题: Re: [COMMIT] Infrastructure Updates 4
* Eric W. Biederman <[EMAIL PROTECTED]> [030903
Eric,
For s2885
8151
| (link0)
CPU0 -- CPU1
| (link2)
8131
|
8111
So the Config.lb should include
northbridge amd/amdk8 "mc0"
pci 0:18.0
pci 0:18.0
pci 0:18.0
pci 0:18.1
pci 0:18.2
pci 0:18.3
* Eric W. Biederman <[EMAIL PROTECTED]> [030903 17:47]:
> First the most basic result I have is that I need to know what all of the
> logical devices that come out of a chip are.
> So off of each logical device I have one or more channels. The only
> way I could think of to describe multiple cha
Stefan Reinauer <[EMAIL PROTECTED]> writes:
> > The way to look at the code is that:
> > - device.c has the logic to enumerate and assign resources to devices and
> busses.
>
> > - pci_device.c has the methods for doing that on pci devices.
> > - hypertransport.c has the methods for doing that wi
ron minnich <[EMAIL PROTECTED]> writes:
> On Wed, 3 Sep 2003, Stefan Reinauer wrote:
>
> > pci 0:18.0
>
> one thing I'd still like to see as long as we are declaring these pci
> slots: why not have the IRQ routing in there?
>
> pci 0:18.o A=B, B=C, C=D, D=A
>
> that way, w
On Wed, 3 Sep 2003, Stefan Reinauer wrote:
> pci 0:18.0
one thing I'd still like to see as long as we are declaring these pci
slots: why not have the IRQ routing in there?
pci 0:18.o A=B, B=C, C=D, D=A
that way, we'd have info to build PIRQ.
any reason not to do this?
r
> The way to look at the code is that:
> - device.c has the logic to enumerate and assign resources to devices and busses.
> - pci_device.c has the methods for doing that on pci devices.
> - hypertransport.c has the methods for doing that with hypertranport devices.
> - northbridge/amd/amdk8/northb
YhLu <[EMAIL PROTECTED]> writes:
> S2880 and S2882 is OK now.
>
> S2885 has some problems. I will try it more..
Sounds good. The code should work for multiple hypertransport chains,
but for some fairly obvious reasons I didn't try it out.
Eric
___
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S2880 and S2882 is OK now.
S2885 has some problems. I will try it more..
-邮件原件-
发件人: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]
发送时间: 2003年9月2日 17:58
收件人: ron minnich
抄送: Stefan Reinauer; LinuxBIOS
主题: Re: [COMMIT] Infrastructure Updates 4
ron minnich <[EMAIL PROTECTED]> writes:
ron minnich <[EMAIL PROTECTED]> writes:
> OK, this commit works for me. Not completely, but well enough to say it's
> good enough.
>
> The only problem is the usual PIRQ fun. I'm going to try to work out a
> reasonable solution given time.
Cool that sounds about right. There is a very real c
OK, this commit works for me. Not completely, but well enough to say it's
good enough.
The only problem is the usual PIRQ fun. I'm going to try to work out a
reasonable solution given time.
ron
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YhLu <[EMAIL PROTECTED]> writes:
> Eric,
>
> Could you explain the Config.lb about northbridge and southbridge PCI
> numbering info?
The Hypertransport chains are numbered exactly like pci busses.
The static information from Config.lb is used just to find the appropriate
methods.
The only chang
Eric,
Could you explain the Config.lb about northbridge and southbridge PCI
numbering info?
Regards
YH
-邮件原件-
发件人: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]
发送时间: 2003年9月2日 12:37
收件人: Stefan Reinauer
抄送: LinuxBIOS
主题: Re: [COMMIT] Infrastructure Updates 4
Stefan Reinauer <[EM
Stefan Reinauer <[EMAIL PROTECTED]> writes:
> * Eric W. Biederman <[EMAIL PROTECTED]> [030902 19:28]:
> > If you want all of your hypertransport devices to be on bus 0, that is
> > feasible but it will take a little more work. Right now each
> > hypertranport chain get's it's own bus.
>
> What i
OK. With this update I start taking advantage of the infrastructure changes
I have been making with the merged trees to dynamically allocate superio
device resources, and to enumerate hypertranport devices.
The code is still rough around the edges but the basic ideas are
there.
If you want all
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