On Mon, 2003-12-01 at 00:47, Denis Dowling wrote:
Hi Svante,
- Original Message -
From: Svante Signell [EMAIL PROTECTED]
To: ron minnich [EMAIL PROTECTED]
Cc: Takeshi Sone [EMAIL PROTECTED]; [EMAIL PROTECTED]
Sent: Monday, December 01, 2003 10:14 AM
Subject: Re: Level 2 cache
On Mon, Dec 01, 2003 at 12:14:14AM +0100, Svante Signell wrote:
No speed-up seen. Extremely slow as before. Any hints? mtrr is OK, I
believe. Is it the microcode??
You could try the microcode driver of Linux or code from LinuxBIOS.
3. How to create a kernel module consisting of more than one
I have now made a small kernel module based on l2_cache.c giving the
following output:
Nov 30 17:46:56 cl-dual kernel: Configuring L2 cache...CPU signature of
6b0 so no L2 cache configuration
Nov 30 17:46:56 cl-dual kernel: Enable Cache
Nov 30 17:46:56 cl-dual kernel: done.
Nov 30 17:46:56
Hi Svante,
- Original Message -
From: Svante Signell [EMAIL PROTECTED]
To: ron minnich [EMAIL PROTECTED]
Cc: Takeshi Sone [EMAIL PROTECTED]; [EMAIL PROTECTED]
Sent: Monday, December 01, 2003 10:14 AM
Subject: Re: Level 2 cache activation code?
I have now made a small kernel module
Do I need to use gcc-2.95.x instead of gcc-3.3.2 to make the inline
assembly run OK? Or is there something about 16bit mode versus 32bit
mode?
On Sun, 2003-11-16 at 11:14, Svante Signell wrote:
I did boot another kernel and for that kernel there was one entry for
mtrr, so this seems to work.
what I did to test this code was to build a kernel module for my linux,
with this code inside, and insmod the kernel module.
ron
___
Linuxbios mailing list
[EMAIL PROTECTED]
http://www.clustermatic.org/mailman/listinfo/linuxbios
I did boot another kernel and for that kernel there was one entry for
mtrr, so this seems to work. However, now I have tried executing both
the mtrr and cache activation code, and when coming to any inline
assembly code the program exits with a segfault :( All commented out
calls have been tried
On Fri, Nov 14, 2003 at 10:46:00PM +0100, Svante Signell wrote:
# Faulty system:
cat /proc/mtrr
cat: /proc/mtrr: No such file or directory
I guess the BIOS does not initialize the MTRR, and all RAM is uncached.
(MTRR is the registers that tell CPU where to cache)
--
Takeshi
On Sun, 16 Nov 2003, Takeshi Sone wrote:
On Fri, Nov 14, 2003 at 10:46:00PM +0100, Svante Signell wrote:
# Faulty system:
cat /proc/mtrr
cat: /proc/mtrr: No such file or directory
I guess the BIOS does not initialize the MTRR, and all RAM is uncached.
(MTRR is the registers that tell
Hi,
I have now run the lmbench3-0-a3 tests. For the correctly working 1.4
GHz Tualatin CPU the latency numbers shows jumps from 2ns to 6ns at 16k
array size and from 6ns to 120ns at 265k array size. I assume this
indicates correctly working level 1 and 2 caches.
For the erroneous motherboard
ron minnich wrote:
On Fri, 14 Nov 2003, Svante Signell wrote:
I have now run the lmbench3-0-a3 tests. For the correctly working 1.4
GHz Tualatin CPU the latency numbers shows jumps from 2ns to 6ns at 16k
array size and from 6ns to 120ns at 265k array size. I assume this
indicates correctly
On Fri, 2003-11-14 at 08:41, Takeshi Sone wrote:
On Fri, Nov 14, 2003 at 08:26:55AM +0100, Svante Signell wrote:
For the erroneous motherboard with a 1.3GHz Tualatin CPU the numbers are
around 400ns independent of array size. The only thing changig is that
the latency numbers increase to
I still do get a segfault when trying to activate the L2 cache, in the
cache_enable() inline assembly routine in l2_cache.c Anything else
neeeded to run this program inside GNU/Linux
On Fri, 2003-11-07 at 15:42, steven james wrote:
Greetings,
Yes, anything non 0 is true. Testing that way (or
Greetings,
Yes, anything non 0 is true. Testing that way (or if(res0) when the
function is to return a count) generally helps to catch wierdness (in the
bad old days, some functions returned -errno or even errno on error but
always 0 on success, this catches all of those cases).
G'day,
sjames
Hi,
Sorry for taking up this thread again but now I have made a test of the
l2_cache activation code and have some further questions.
The files put together to make things build are l2_cache.c, printk.c,
vsprintf.c, subr.c and corresponding header files from the linuxbios CVS
tree. For subr.c I
Greetings,
To run that code inside linux, you need to add a call to iopl to allow
direct hardware access like:
res = iopl(3);
if(res) {
report_error();
exit(-1);
}
or something to that effect.
G'day,
sjames
On Thu, 6 Nov 2003, Svante Signell wrote:
Hi,
Sorry for taking up
On Thu, 6 Nov 2003, Svante Signell wrote:
Sorry for taking up this thread again but now I have made a test of the
l2_cache activation code and have some further questions.
you don't need this code any more. The last processor it mattered for is
long dead. I am not removing it but if you are
Ron,
Thank you for your reply. Maybe there is hope after all.
On Wed, 2003-10-01 at 01:34, ron minnich wrote:
On Tue, 30 Sep 2003, Svante Signell wrote:
i) Does this code work for 440BX motherboards?
it's processor-dependent, 440bx or not is not an issue.
Thanks for the info. To clarify
On Wed, 1 Oct 2003, Svante Signell wrote:
i) Does LinuxBIOS work for 440BX-based mother-boards, single and dual?
Downloading the code from CVS shows support for Intel L440GX+ and a
patch for linux-2.4.13, not 440BX or kernels later than 2.4.13. Also, I
did not find anything about MSI
Hello,
I have recently upgraded my dual MSI-6120 from 2xCeleron (Mendocino)
[EMAIL PROTECTED] with 2xMSI-6905 slot 370 to slot 1 adapters to one Celeron2
1.3GHz (Tualatin) using a Slot-T adapter card. The plan is to equip the
mobo with 2xPIII or preferably 2xVIA C3 Nehemiah (when SMP capable).
On Tue, 30 Sep 2003, Svante Signell wrote:
i) Does this code work for 440BX motherboards?
it's processor-dependent, 440bx or not is not an issue.
ii) Is it possible to extract this code and try out after the kernel has
booted (slowly), to verify my assumption?
yes, we tested it that way.
21 matches
Mail list logo
