--- Eric W. Biederman ebiederman@lnxi.com wrote:
Socket 370 is the first socket that Intel denied the
clone
manufacturers from using I believe. So the choice
in cpus
should be fairly small.
There are not any pin changes for the various speeds
of PIII. Well at least as far as 733Mhz. Our
I need to start looking at moving the 440bx stuff to
V2. The part I'm most concerned about is re-writing
the ram init code.
Is it possible to use the V2 structure but graft in
the assembly output from V1? Then as time permits I
can go back and re-write those routines.
Tell me again which is
Richard Smith [EMAIL PROTECTED] writes:
I need to start looking at moving the 440bx stuff to
V2. The part I'm most concerned about is re-writing
the ram init code.
Is it possible to use the V2 structure but graft in
the assembly output from V1? Then as time permits I
can go back and
--- Eric W. Biederman ebiederman@lnxi.com wrote:
Something like the via epia, q-emu should be ok. I
don't really
know as I have not looked at the simple embedded
case lately. In the
last round of cleanups I'm pretty certain we managed
to purge the
worst of the bad examples from the tree
On Wed, 12 Jan 2005, Richard Smith wrote:
Is it possible to use the V2 structure but graft in
the assembly output from V1? Then as time permits I
can go back and re-write those routines.
bite the bullet. Just write the C. I've tried both ways and the C is just
plain easier.
I would go
On Wed, 12 Jan 2005, Richard Smith wrote:
IIRC the q-emu wasn't really complete enough for my
purposes. I'll start with epia and go from there.
sorry, richard, I misunderstood your question. Yeah, try the epia.
ron
___
Linuxbios mailing list
--- Ronald G. Minnich rminnich@lanl.gov wrote:
bite the bullet. Just write the C. I've tried both
ways and the C is just
plain easier.
The problem with that is that it requires me to
actually go _understand_ the code. *grin* I fixed a
few bugs in the origial asm code but most of it
On Wed, 12 Jan 2005, Richard Smith wrote:
Dose either this one or the epia read the SPD eproms
and set the registers accordingly?
you mean does the EPIA read the SPD? Yes it does, and
somebody recently fixed a bunch of bugs so it does a better job that it
used to.
ron
I don't understand the cpu naming scheme in the
cpu/intel dirctory.
Our board uses a PIII Celeron in a PGA socket 370 @
400 Mhz
should I just call the directory socket_PGA370 or do I
need to add speed info? What about the Celeron,
non-celeron difference?
=
Richard A. Smith
Bitworks, Inc.
Richard Smith [EMAIL PROTECTED] writes:
I don't understand the cpu naming scheme in the
cpu/intel dirctory.
Our board uses a PIII Celeron in a PGA socket 370 @
400 Mhz
should I just call the directory socket_PGA370 or do I
need to add speed info? What about the Celeron,
non-celeron
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