On Tue, 26 Nov 2002, Ronald G. Minnich wrote:
> On Tue, 26 Nov 2002, Adam Sulmicki wrote:
>
> > well it always could be intermediate solution. In this way we only have 4
> > data structures and no functions.
>
> sounds like we need a union, with a tag, and then the descriptors. In the
> limit,
On Tue, 26 Nov 2002, Adam Sulmicki wrote:
> well it always could be intermediate solution. In this way we only have 4
> data structures and no functions.
sounds like we need a union, with a tag, and then the descriptors. In the
limit, the tag can be TAG_CODE, meaning you have to call the attache
> well, looks like my beautiful theory just got killed by a brutal gang of
> facts. Now it's somebody else's turn to figure this out :-)
well it always could be intermediate solution. In this way we only have 4
data structures and no functions.
--
Adam Sulmicki
http://www.eax.com The Suprem
On 26 Nov 2002, Christer Weinigel wrote:
> "Ronald G. Minnich" <[EMAIL PROTECTED]> writes:
>
> > One thing we should keep in mind for the shadow ram thing:
> > Just about every chipset I have seen has shadow ram registers that can
> > correctly be set with the following info:
> >
> > VendorID,
> > One thing we should keep in mind for the shadow ram thing:
> > Just about every chipset I have seen has shadow ram registers that can
> > correctly be set with the following info:
> >
> > VendorID, DeviceID, Function, register, AndMask, OrMask.
> >
> > ...
> > I haven't stumbled across a ch
"Ronald G. Minnich" <[EMAIL PROTECTED]> writes:
> One thing we should keep in mind for the shadow ram thing:
> Just about every chipset I have seen has shadow ram registers that can
> correctly be set with the following info:
>
> VendorID, DeviceID, Function, register, AndMask, OrMask.
>
> Thi
"Ronald G. Minnich" <[EMAIL PROTECTED]> writes:
> On 25 Nov 2002, Eric W. Biederman wrote:
>
> > Except for the Athlons? Which control this in the CPU?
>
> yes but ... that's a test for cpuid.
>
> > For the most part we should just enable these area in LinuxBIOS.
>
> For motherboards that w
On 25 Nov 2002, Eric W. Biederman wrote:
> Except for the Athlons? Which control this in the CPU?
yes but ... that's a test for cpuid.
> For the most part we should just enable these area in LinuxBIOS.
For motherboards that will work if we do that. There are still weirdo ones
out there that
"Ronald G. Minnich" <[EMAIL PROTECTED]> writes:
> One thing we should keep in mind for the shadow ram thing:
> Just about every chipset I have seen has shadow ram registers that can
> correctly be set with the following info:
>
> VendorID, DeviceID, Function, register, AndMask, OrMask.
>
> Thi
One thing we should keep in mind for the shadow ram thing:
Just about every chipset I have seen has shadow ram registers that can
correctly be set with the following info:
VendorID, DeviceID, Function, register, AndMask, OrMask.
This rapidly leads to a simple table something like this:
struct
steven james <[EMAIL PROTECTED]> writes:
> Greetings,
>
> I was thinking of locating the function table somewhere in ram. Perhaps it
> and the code itself could go in the 64 K at 0x10 and A20 could be
> turned on to access that small highmem area with the segment register set
> at 0x. I h
11 matches
Mail list logo
