On Tue, Oct 19, 2004 at 12:12:50PM +0800, Liu Tao wrote:
Or does the interrupt router in pirq table only
responses of legacy 32bitPCI/ISA devices, and Linux
handles all the AMD8131?
Forgive my ignorance, but doesn't the fact that PCI-X is all message
signaled interrupts obviate the need for a
.
-Original Message-
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]
Sent: Tuesday, October 19, 2004 1:17 PM
To: Liu Tao
Cc: YhLu; Dave Aubin; [EMAIL PROTECTED]
Subject: Re: PCI IRQ tables
On Tue, Oct 19, 2004 at 12:12:50PM +0800, Liu Tao wrote:
Or does the interrupt router in pirq table only
Message-
From: Liu Tao [mailto:[EMAIL PROTECTED]
Sent: Monday, October 18, 2004 9:13 PM
To: YhLu
Cc: Dave Aubin; [EMAIL PROTECTED]
Subject: Re: PCI IRQ tables
Hello,
Thanks for your answer:)
But I'm still not very clear of the PCI interrupt
routing for legacy PIC mode on AMD64. For example
]
Subject: Re: PCI IRQ tables
YhLu wrote:
SMP or single CPU?
If SMP, and io apci is enabled, you may only focus on mptable.c and
irq-tables.c may only contain device that point to the peer roots bus.
YH
How about single CPU with IO-APIC enabled in linux?
We are designing a new AMD64
Hello,
Thanks for your answer:)
But I'm still not very clear of the PCI interrupt
routing for legacy PIC mode on AMD64. For example in
s2885 mainboard the pirq table specifys the AMD8111
as the interrupt router (bus1 dev4 fn3), then how
does the interrupt from the PCIX devices on AMD8131
routed to
you can find the definition of $PIR standard at microsoft -- I always lose
it, but google always finds it.
ron
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PCI IRQ specification:)
http://www.microsoft.com/whdc/archive/pciirq.mspx
-Original Message-
From: Ronald G. Minnich [mailto:[EMAIL PROTECTED]
Sent: Thursday, September 30, 2004 3:49 PM
To: Dave Aubin
Cc: [EMAIL PROTECTED]
Subject: RE: PCI IRQ tables
you can find the definition
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