Greetings,
It's been a while since I've looked at it, but when I last looked, it did
sometimes need power cycled to restart. I worked around that by making the
kernel reboot by writing 0x0e to port 0xcf9. That causes the southbridge
to do a 3 second power off.
G'day,
sjames
On Fri, 5 Nov 2004,
Does anyone know if the raminit.c under intel/E7501 is stable enough? I am
having a problem with the system reseting when it jumps to the first address
in the ram. Could the procedures of writing NorthBrige registers have
problems?
thanks,
Gin
___
L
On Tue, 28 Sep 2004, zhu shi song wrote:
> (1)I disabled i786/earlymtrr, RAM NOP ok
> (2)After executing original bios, RAM NOP couldn't
> pass.
sounds like it, MTRRs should really not be on during DDR init in the DRAM
space. What are your current settings?
ron
___
(1)I disabled i786/earlymtrr, RAM NOP ok
(2)After executing original bios, RAM NOP couldn't
pass.
Maybe I should set mtrr correctly.
zhu
___
Do you Yahoo!?
Declare Yourself - Register online to vote today!
http://vote.yahoo.com
___
Stefan Reinauer <[EMAIL PROTECTED]> writes:
> * Stefan Reinauer <[EMAIL PROTECTED]> [040319 16:50]:
> > low = spd_read_byte(device, 6); /* (low byte) */
> > if (low < 0) goto hw_err;
> > value = value | (low & 0xff);
> > if ((value != 72) && (value &= 64)) goto val_
* Stefan Reinauer <[EMAIL PROTECTED]> [040319 16:50]:
> low = spd_read_byte(device, 6); /* (low byte) */
> if (low < 0) goto hw_err;
> value = value | (low & 0xff);
> if ((value != 72) && (value &= 64)) goto val_err;
> ^^^
> It s
* Stefan Reinauer <[EMAIL PROTECTED]> [040319 15:38]:
> Ram1.00
> Ram2.00
> Bad SPD value
low = spd_read_byte(device, 6); /* (low byte) */
if (low < 0) goto hw_err;
value = value | (low & 0xff);
if ((value != 72) && (value &= 64)) goto val_err;
Excerpt from current solo build:
LinuxBIOS-1.1.6.0-Fallback Fr Mär 19 14:43:18 CET 2004 starting...
setting up resource mapdone.
ht reset -
On Tue, 21 Oct 2003, SONE Takeshi wrote:
> SF CVS is working very well these days.. no connection resets,
> less delay, faster updates.
I'll check later today and see if I forgot to commit ...
ron
___
Linuxbios mailing list
[EMAIL PROTECTED]
http://ww
* ron minnich <[EMAIL PROTECTED]> [031021 15:55]:
> No, these are in CVS AFAIK; the problem is that you are suffering the
> 24-hour delay again.
If so, please use http://snapshots.linuxbios.org/
Stefan
--
ARCHITECTURE TEAM
SUSE LINUX AG
___
Lin
On Tue, Oct 21, 2003 at 07:55:20AM -0600, ron minnich wrote:
> On Tue, 21 Oct 2003, SONE Takeshi wrote:
>
> >
> > src/mainboard/via/epia/Config.lb:
> > * chooses COMPATIBILITY mode rather than native mode
> > * more appropriate romcc options
> >
> > src/southbridge/via/vt8231/vt8231.c:
On Tue, 21 Oct 2003, SONE Takeshi wrote:
>
> src/mainboard/via/epia/Config.lb:
> * chooses COMPATIBILITY mode rather than native mode
> * more appropriate romcc options
>
> src/southbridge/via/vt8231/vt8231.c:
> * proper interpretation of enable_native_ide
>
> src/mainboard/via
On Mon, Oct 20, 2003 at 03:48:18PM -0600, ron minnich wrote:
> Takeshi, I have put your changes in (earlymtrr.c, etc.) except for
> raminit. We should talk about that offline, but I want to better
> understand what you are doing, since two slots was working for me.
Besides raminit, some importan
Takeshi, I have put your changes in (earlymtrr.c, etc.) except for
raminit. We should talk about that offline, but I want to better
understand what you are doing, since two slots was working for me.
ron
___
Linuxbios mailing list
[EMAIL PROTECTED]
htt
Attached patch fixes IDE compatibility mode (so FILO works),
and RAM initialization, so the DIMM on the second slot works.
SPD is not used by this patch, we have to figure out how to
type MA mapping by SPD (see the comment in the code).
Maybe I will work on SPD-based RAM timing.
earlymtrr.c should
On Tue, 22 Jul 2003, Andrew Ip wrote:
> > SPD contents is very easy to access. The epia-m code is including
> > src/northbridge/via/vt8623/raminit.inc
> > to initialize ram. I found problems with this, the jedec ddr init spec
> > sequence calls for reads of the ddr memory, this source actually doe
Hi Dave,
> As a recap I was trying to get 2 specific DDR modules working with the
> epia-m. One has ICT chips and the other has GET chips. The ICT module works
> with the hardcoded dram configuration, but the GET module doesn't.
> ICT = 1 bank 128M colbits = 10
> GET = 2 banks 64M colbits = 9
Same
As a recap I was trying to get 2 specific DDR modules working with the
epia-m. One has ICT chips and the other has GET chips. The ICT module works
with the hardcoded dram configuration, but the GET module doesn't.
ICT = 1 bank 128M colbits = 10
GET = 2 banks 64M colbits = 9
I had tried hardcoding
18 matches
Mail list logo
