Dear LinuxBIOS readers!
This is the automated build check service of LinuxBIOS.
The developer uwe checked in revision 2687 to
the LinuxBIOS source repository and caused the following
changes:
Change Log:
Add missing license headers, minor cosmetic fixes in existing headers.
Signed-off-by: Uwe
Peter Stuge wrote:
On Tue, May 22, 2007 at 02:23:30PM +0100, Ceri wrote:
Comments pls?
Have you had a chance to test it?
+ NBXCFG, 0x, 0xff00a00c,PCI_REGISTER_32BIT,
[..]
+ FDHC, 0x00, 0x00, PCI_REGISTER_8BIT,
+ for (i = 0; i max; i += 4) {
+
Peter Stuge wrote:
On Tue, May 22, 2007 at 12:25:43PM +0100, Marcelo Coelho wrote:
So, if you want to pass it into a function you have to define the
function with the parameter as being a pointer (and a good practice
would be also pass the size of the array).
On Tue, May 22, 2007 at
On Tue, May 22, 2007 at 02:23:30PM +0100, Ceri wrote:
Comments pls?
Have you had a chance to test it?
+ NBXCFG, 0x, 0xff00a00c,PCI_REGISTER_32BIT,
[..]
+ FDHC, 0x00, 0x00, PCI_REGISTER_8BIT,
+ for (i = 0; i max; i += 4) {
+
On Tue, May 22, 2007 at 09:15:54AM +0200, Sven Kapferer wrote:
This is strange, because the compiler option -DK8_REV_F_SUPPORT='1' was
already set by including cpu/amd/socket_AM2. I just verified this by
compiling the gigabyte board with an svn version that doesn't include
your changes to
On Mon, May 21, 2007 at 02:12:52PM -0700, yhlu wrote:
NAK.
Already defined src/cpu/amd/socket_AM2/Config.lb.
and your MB Config.lb will include that with
chip cpu/amd/socket_AM2
Yes, you're quite right, my patch is not necessary.
Thanks,
Ward.
--
Ward Vandewege [EMAIL PROTECTED]
Free
On Mon, May 21, 2007 at 10:51:05PM +0200, Peter Stuge wrote:
On Mon, May 21, 2007 at 04:29:31PM -0400, Ward Vandewege wrote:
The Gigabyte m57sli-s4 board supports Rev. F CPUs.
Signed-off-by: Ward Vandewege [EMAIL PROTECTED]
r2683
This should be reverted. Should I send in another patch
On Tue, May 22, 2007 at 05:05:59PM +0200, Stefan Reinauer wrote:
This should be reverted. Should I send in another patch for that?
Not necessary. svn diff -r 2683:2682
Thanks. I should have backed this out but you got to it before me.
//Peter
--
linuxbios mailing list
Dear LinuxBIOS readers!
This is the automated build check service of LinuxBIOS.
The developer stepan checked in revision 2688 to
the LinuxBIOS source repository and caused the following
changes:
Change Log:
reverting 2683, NAK by YhLu, patch not necessary.
Signed-off-by: Stefan Reinauer
Peter Stuge wrote:
On Mon, May 21, 2007 at 10:41:16PM +0100, Ben Hewson wrote:
on the down side I am still experiencing the odd random hang
After power off/power on or after reset?
I mostly notice it after a power on as I usually power off after
reflashing the ROM. Once it hangs
Indrek Kruusa wrote:
Ühel kenal päeval (teisipäev 22 mai 2007 1:17 pm) kirjutas Uwe Hermann:
On Mon, May 21, 2007 at 04:56:20PM -0600, Marc Jones wrote:
we have two similar directories in svn:
src/southbridge/amd/cs5536
src/southbridge/amd/cs5536_lx
Why do we have two? Are they
FYI, for those of you working with the AMD Geode GX1. The databook has
been posted for general consumption.
http://www.amd.com/us-en/ConnectivitySolutions/ProductInformation/0,,50_2330_9863_9907,00.html
Marc
--
Marc Jones
Senior Software Engineer
(970) 226-9684 Office
mailto:[EMAIL PROTECTED]
On Tue, May 22, 2007 at 12:04:15PM -0600, Marc Jones wrote:
FYI, for those of you working with the AMD Geode GX1. The databook
has been posted for general consumption.
http://www.amd.com/us-en/ConnectivitySolutions/ProductInformation/0,,50_2330_9863_9907,00.html
Really awesome! :)
//Peter
I have just had a look at dmesg after booting from LinuxBios and have
noticed the following.
standard EPIA board.
11-DMI not present.
12:ACPI: RSDP (v000 VIA601) @ 0x000f67c0
13:ACPI: Unable to map RSDT
14-Allocating PCI resources starting at 3000 (gap:
On Fri, May 11, 2007 at 12:29:39PM -0700, yhlu wrote:
On 5/11/07, Carl-Daniel Hailfinger [EMAIL PROTECTED] wrote:
A few interesting differences between the dumps:
* LinuxBIOS has subsystem vendor/id 1022:2b80 for all devices
- Bug or feature?
you could change it in MB Option.lb. I
On Tue, May 22, 2007 at 01:37:25PM -0700, yhlu wrote:
On 5/22/07, Ward Vandewege [EMAIL PROTECTED] wrote:
The Gigabyte vendor id is 0x1458; how can I find out what
MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID should be set to for this board?
boot into linux with Normal BIOS. (---sorry to say that
Ward Vandewege wrote:
On Tue, May 22, 2007 at 01:37:25PM -0700, yhlu wrote:
On 5/22/07, Ward Vandewege [EMAIL PROTECTED] wrote:
The Gigabyte vendor id is 0x1458; how can I find out what
MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID should be set to for this board?
boot into linux with Normal BIOS.
Hi,
On Sat, May 19, 2007 at 12:13:26AM -0500, Jonathan King wrote:
Hello I just joined the list and I am truly excited to hear that Nvidia is
cooperating with the MCP55 chipset. I have an ASUS M2N-E motherboard
and
here are my stats.
That's not supported yet, unfortunately. As it uses
Hi,
Wondering if you can test all 4 SATA ports, i don't think anyone has
more than 2 of 4 working.
I'm working on a Tyan S2865 board, similar except the SuperIO chip. I'm
having trouble with only one of four PCI slots generating interrupts. I
wonder if you can try a PCI network card or
Indrek Kruusa wrote:
Could it be that setup for one LX board (amd/norwitch) does something very
special that prevents this LB ROM to run (to some extent) on another LX
board
(artecgroup/dbe61)? It stops at postcode 0x10 (Entry into protected mode). I
suppose that whatever LX target rom
On 5/21/07, Indrek Kruusa [EMAIL PROTECTED] wrote:
Could it be that setup for one LX board (amd/norwitch) does something very
special that prevents this LB ROM to run (to some extent) on another LX board
(artecgroup/dbe61)? It stops at postcode 0x10 (Entry into protected mode). I
suppose that
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