On Sat, 2007-05-26 at 19:26 -0700, Russ Whitaker wrote:
On Sun, 27 May 2007, Luc Verhaegen wrote:
On Sat, May 26, 2007 at 05:29:28PM +0200, Stefan Reinauer wrote:
No, this is purely to get 640x480 textmode to work on the CRT
Shouldn't that be vga video mode 3, 720x400 res, which
Just a couple quick responses, I'll get to work on changes as soon as I
can coax fedora into working correctly again. minicom.cap attached, I
forgot it before.
On Sat, 2007-05-26 at 15:29 +0200, Uwe Hermann wrote:
Also, the i82801aa is almost completely copy and pasted from the
i82801ca, with
On Sat, May 26, 2007 at 07:26:54PM -0700, Russ Whitaker wrote:
On Sun, 27 May 2007, Luc Verhaegen wrote:
On Sat, May 26, 2007 at 05:29:28PM +0200, Stefan Reinauer wrote:
No, this is purely to get 640x480 textmode to work on the CRT
Shouldn't that be vga video mode 3, 720x400 res,
Poll: do we want i810 or rather i82810? For the southbridges we use the
full names (e.g. i82801aa), why don't we do the same with the
northbridges?
(yes, that would also change i440bx to i82443bx)
Hello,
Yes I also agree, as far as Intel chips, it would aviod confusion to
just use their
Hi I have littel trouble with this mainboard.
First: Is this normal?
shnip
Capability: 0x10 @ 0x80
PCI: 00:01.0 [1106/8601] enabled
PCI: devfn 0x10, bad id 0x
PCI: devfn 0x18, bad id 0x
PCI: devfn 0x20, bad id 0x
PCI: devfn 0x28, bad id 0x
PCI: devfn 0x30, bad id
On Sun, May 27, 2007 at 04:48:51AM -0400, Corey Osgood wrote:
#define I82801AA 1
Agreed, as long as no further fixup is necessary. Perhaps I'll just hold
onto this patch until I can fully test out the southbridge function, or
else we could commit as-is and I'll do some cleanup later.
I
Looking at the user manual, probably the only difference between the
EPIA and EPIA V is that the EPIA has 2 IDE and no floppy where as the
EPIA V loses 1 IDE for the floppy connector. Same chipsets. I am
surprised it doesn't get further.
I get all of the PCI: devfn 0x10, bad id 0x
Author: uwe
Date: 2007-05-27 23:43:58 +0200 (Sun, 27 May 2007)
New Revision: 2700
Modified:
trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb.c
trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb.h
Log:
Init for the Intel 82371EB southbridge: make all ROM/BIOS regions
On Sun, May 27, 2007 at 10:52:19PM +0200, Stefan Reinauer wrote:
* Uwe Hermann [EMAIL PROTECTED] [070527 22:45]:
Other entries on the 440BX TODO list are:
- Make RAM init generic, not hardcoded to the S1846
This patch was sent around by Alfred Wanga on april 30th
Yep, needs some changes
Dear LinuxBIOS readers!
This is the automated build check service of LinuxBIOS.
The developer uwe checked in revision 2700 to
the LinuxBIOS source repository and caused the following
changes:
Change Log:
Init for the Intel 82371EB southbridge: make all ROM/BIOS regions
accessible (but not
See patch.
Tested on Tyan S1846, works fine.
Uwe.
--
http://www.hermann-uwe.de | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
Lower the RAM init delays we use on the Intel 440BX.
As per JEDEC, we should wait 200us until voltages and
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