2007/5/31, Juergen Beisert [EMAIL PROTECTED]:
Maybe a silly question: Isn't it that PCI needs initialization before
we could access it? How could we get there when the processor is
fetching the 1st instruction?
In this case the ROM device is connected to the PCI bus, but not connected
Hi there,
The LinuxBIOS booth at the Linux Tag in Berlin is a great success. Thank
you very much to all people contributing their time and effort here at
the booth to make this possible, and thank you very much to all
visitors. It has been a couple of very nice and successful days for the
Stefan Reinauer wrote:
Hi there,
The LinuxBIOS booth at the Linux Tag in Berlin is a great success. Thank
you very much to all people contributing their time and effort here at
the booth to make this possible, and thank you very much to all
visitors. It has been a couple of very nice and
The attached patch is a unified version of the current ports of the
i82801 series currently in LinuxBIOS. Since most of the ports are nearly
identical, I've taken for each file and chosen the cleanest or best
version of the code, then checked over the datasheets to *some* of the
series, including
Corey Osgood wrote:
Testing on other chips can be done at this point as well, this is tested
and working on one model, the i82801aa.
Whoops, forgot to mention, usage is pretty straightforward. In your
mainboard's Options.lb, add
uses I82801_MODEL
uses I82801yourmodel
default I82810_MODEL =
Author: uwe
Date: 2007-06-02 14:28:58 +0200 (Sat, 02 Jun 2007)
New Revision: 341
Modified:
LinuxBIOSv3/Makefile
LinuxBIOSv3/arch/x86/Makefile
Log:
Cosmetic fixes (trivial).
Signed-off-by: Uwe Hermann [EMAIL PROTECTED]
Acked-by: Uwe Hermann [EMAIL PROTECTED]
Modified:
On Saturday 02 June 2007 10:25, Yu-ning Feng wrote:
Please check whether I have understood correctly.
The processor lauches a cycle with address = 0x_FFF0. The north
bridge chipset explains this address. In this case, it signals the
read line and chip select line which connect the ROM
Juergen,
Can you please explain which chipset northbridge does this? I've never
seen one that uses the PCI bus in this fashion, but I'd like to know if
there is one.
http://www.intel.com/design/chipsets/440/documentation.htm
Everyone, please look at Intel 440BX chipset docs for a clear
Sorry to jump in a bit late here, but for parallel flash, what about
using a NIC with a boot ROM socket? I've used that for both PLCC32 and
DIP32 parts.
Regards,
Jeremy
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On Thu, May 31, 2007 at 01:43:43AM +0200, Stefan Reinauer wrote:
Index: Makefile
===
--- Makefile(Revision 338)
+++ Makefile(Arbeitskopie)
doxygen:
$(Q)$(DOXYGEN) util/doxygen/Doxyfile.LinuxBIOS
Author: uwe
Date: 2007-06-03 01:55:17 +0200 (Sun, 03 Jun 2007)
New Revision: 2706
Modified:
trunk/LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536.c
Log:
The UART disable code was causing a hang and was worked around with a
return that skipped the disable code. This patch removes the return and
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