Kiran Patil wrote:
On Dec 28, 2007 7:30 PM, Carl-Daniel Hailfinger
[EMAIL PROTECTED]
mailto:[EMAIL PROTECTED] wrote:
On 28.12.2007 14:29, Kiran Patil wrote:
MSI MS-7250 VER:2.2 (K9N Ultra) motherboard is not
detecting
SST49LF004A/B chip.
I am
On Dec 29, 2007 2:41 PM, Corey Osgood [EMAIL PROTECTED] wrote:
Kiran Patil wrote:
On Dec 28, 2007 7:30 PM, Carl-Daniel Hailfinger
[EMAIL PROTECTED]
mailto:[EMAIL PROTECTED] wrote:
On 28.12.2007 14:29, Kiran Patil wrote:
MSI MS-7250 VER: 2.2 (K9N Ultra)
Author: hailfinger
Date: 2007-12-29 11:14:38 +0100 (Sat, 29 Dec 2007)
New Revision: 3025
Modified:
trunk/util/flashrom/flashchips.c
Log:
Add 25VF016B support to flashrom. Untested, but verified against the
data sheet.
Signed-off-by: Carl-Daniel Hailfinger [EMAIL PROTECTED]
Acked-by: Corey
Author: hailfinger
Date: 2007-12-29 11:14:38 +0100 (Sat, 29 Dec 2007)
New Revision: 3025
Modified:
trunk/util/flashrom/flashchips.c
Log:
Add 25VF016B support to flashrom. Untested, but verified against the
data sheet.
Signed-off-by: Carl-Daniel Hailfinger [EMAIL PROTECTED]
Acked-by: Corey
Author: hailfinger
Date: 2007-12-29 11:15:58 +0100 (Sat, 29 Dec 2007)
New Revision: 3026
Modified:
trunk/util/flashrom/spi.c
Log:
Print the chip status register for all SPI chips on probe if verbose
output is specified.
Pretty-print the chip status register (including block lock information)
Author: hailfinger
Date: 2007-12-29 11:15:58 +0100 (Sat, 29 Dec 2007)
New Revision: 3026
Modified:
trunk/util/flashrom/spi.c
Log:
Print the chip status register for all SPI chips on probe if verbose
output is specified.
Pretty-print the chip status register (including block lock information)
On 29.12.2007 06:07, Corey Osgood wrote:
Carl-Daniel Hailfinger wrote:
Add 25VF016B support to flashrom. Untested, but verified against the
data sheet.
Signed-off-by: Carl-Daniel Hailfinger [EMAIL PROTECTED]
Acked-by: Corey Osgood [EMAIL PROTECTED]
Thanks, r3025.
Regards,
On 29.12.2007 06:23, Corey Osgood wrote:
Looks good here:
Acked-by: Corey Osgood [EMAIL PROTECTED]
On Dec 28, 2007 7:30 AM, Carl-Daniel Hailfinger wrote:
On 17.12.2007 21:33, Carl-Daniel Hailfinger wrote:
Print the chip status register for all SPI chips on probe if verbose
output
On 28.12.2007 13:25, Carl-Daniel Hailfinger wrote:
On 18.12.2007 00:57, Carl-Daniel Hailfinger wrote:
All SPI chips mentioned in flashchips.c had their sector size listed as
page size. Fix that. Page size is uniform 256 bytes for SPI.
A sector/block size field in struct flashchip would be
Urbez Santana Roma wrote:
Thanks for answer Rudolf, the CPU can SSE and SSE2, when runs with
normal BIOS the instruction movd %eax,%xmm0 works in, but if the
linuxbios need working with sse and sse2 with a microKernel for
example, this instruction produces a exception.
My contents of the
Hello
Advance happy New year..
ASRock K8Upgrade-VM800 motherboard is detecting SST49LF004A/B chip,but we
are unable to write(flash).
what is the procedure for writting programe on
SST49LF004A/B chip.
we got a information like, remove the SST chip from its socket, strip the
Carl-Daniel Hailfinger wrote:
On 28.12.2007 13:25, Carl-Daniel Hailfinger wrote:
On 18.12.2007 00:57, Carl-Daniel Hailfinger wrote:
All SPI chips mentioned in flashchips.c had their sector size listed as
page size. Fix that. Page size is uniform 256 bytes for SPI.
A
Dear LinuxBIOS readers!
This is the automated build check service of LinuxBIOS.
The developer hailfinger checked in revision 3025 to
the LinuxBIOS source repository and caused the following
changes:
Change Log:
Add 25VF016B support to flashrom. Untested, but verified against the
data sheet.
Author: hailfinger
Date: 2007-12-29 12:05:59 +0100 (Sat, 29 Dec 2007)
New Revision: 3027
Modified:
trunk/util/flashrom/flashchips.c
Log:
All SPI chips mentioned in flashchips.c had their sector size listed as
page size. Fix that. Page size is uniform 256 bytes for SPI.
A sector/block size
Author: hailfinger
Date: 2007-12-29 12:05:59 +0100 (Sat, 29 Dec 2007)
New Revision: 3027
Modified:
trunk/util/flashrom/flashchips.c
Log:
All SPI chips mentioned in flashchips.c had their sector size listed as
page size. Fix that. Page size is uniform 256 bytes for SPI.
A sector/block size
On 29.12.2007 12:00, Corey Osgood wrote:
Carl-Daniel Hailfinger wrote:
On 28.12.2007 13:25, Carl-Daniel Hailfinger wrote:
On 18.12.2007 00:57, Carl-Daniel Hailfinger wrote:
All SPI chips mentioned in flashchips.c had their sector size listed as
page size. Fix
On 29.12.2007 10:56, Kiran Patil wrote:
Yes I tried it on ASRock motherboard and it is detecting. I am not using
BIOS Savior, instead I am removing the Pm49FL004 chip and inserting the
SST49LF004A/B chip in the Bios socket and after that using flashrom utility
to do further operations.
Hello
Advance happy New year..
ASRock K8Upgrade-VM800 motherboard is detecting SST49LF004A/B chip,but we
are unable to write(flash).
what is the procedure for writting programe on
SST49LF004A/B chip.
we got a information like, remove the SST chip from its socket,
Dear LinuxBIOS readers!
This is the automated build check service of LinuxBIOS.
The developer hailfinger checked in revision 3026 to
the LinuxBIOS source repository and caused the following
changes:
Change Log:
Print the chip status register for all SPI chips on probe if verbose
output is
Dear LinuxBIOS readers!
This is the automated build check service of LinuxBIOS.
The developer hailfinger checked in revision 3027 to
the LinuxBIOS source repository and caused the following
changes:
Change Log:
All SPI chips mentioned in flashchips.c had their sector size listed as
page size.
On Dec 29, 2007 4:54 PM, Carl-Daniel Hailfinger
[EMAIL PROTECTED] wrote:
Is it a SST49LF004A or SST49LF004B? You have to look at the numbers
printed on the chip.
The SST49LF004A variant is FWH only, but the Pm49FL004 is FWH+LPC
capable. That (chip not designed for the board) might be the
On Dec 28, 2007 9:59 PM, Phani Babu Giddi [EMAIL PROTECTED] wrote:
Hello All,
It appears that the DSDT tables and the related ASL files are present for
few boareds in Linux BIOS. If so how are other boards expected to provide
the required DSDT table. Does it has to be taken care either by the
Hi Yhlu,
Thanks for your response.
I was mainly looking at Geode LX based processor boards and associated
chipsets. I dont think that ASL/AML for these boards is available. But my
question was generic, i mean what if I plan to use Linux BIOS for a custom
board and I want to comply with ACPI. In
This patch is an attempt at introducing 4k CAR size granularity for the
generic x86 code. For the old supported CAR sizes, the newly generated
code is equivalent, so it should be a no-brainer.
Add a copyright header to the code, the header is derived from the one
found in the same piece of code
The following mainboards had a file named microcode_updates.c in their
mainboard directories, but the code was not referenced anywhere.
intel/jarrell
dell/s1850
supermicro/x6dhr_ig2
supermicro/x6dhr_ig
supermicro/x6dhe_g2
supermicro/x6dhe_g
Besides that, the contents of these files were either
+ /* Check if it is a continuation ID, this should be a while
loop. */
+ if (id1 == 0x7F) {
+ largeid1 = 8;
+ id1 = *(volatile uint8_t *)(bios + 0x100);
+ largeid1 |= id1;
+ }
+ if (id2 == 0x7F) {
+ largeid2 =
Quoting Corey Osgood [EMAIL PROTECTED]:
Acked-by: Corey Osgood [EMAIL PROTECTED]
how long has it been since we've updated the microcode updates?
No idea, but remember the email below from 12/12/07? Looks like an
update is in order, but I wouldn't know where to start.
Thanks - Joe
Quoting
On Dec 29, 2007 9:00 PM, [EMAIL PROTECTED] wrote:
Quoting Corey Osgood [EMAIL PROTECTED]:
Acked-by: Corey Osgood [EMAIL PROTECTED]
how long has it been since we've updated the microcode updates?
No idea, but remember the email below from 12/12/07? Looks like an
update is in order,
On Dec 29, 2007 2:43 PM, Phani Babu Giddi [EMAIL PROTECTED] wrote:
Let me know what you think about this.
we need someone to figure out ACPI: in other words, how we can do it
in linuxbios (v3 mainly), what the restrictions are, etc.
At the 2006 meeting in hamburg we started on this topic, but
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