Hi Ben,
On Thu, 23 Jul 2009 15:59:47 +1000 Benjamin Herrenschmidt
wrote:
>
> @@ -480,3 +508,4 @@
> #endif /* 403GCX */
> #endif /* __ASM_POWERPC_REG_BOOKE_H__ */
> #endif /* __KERNEL__ */
> +
I know I am being trivial here ... :-)
--
Cheers,
Stephen Rothwells...@canb.auu
Hi Ben,
On Thu, 23 Jul 2009 15:59:46 +1000 Benjamin Herrenschmidt
wrote:
>
> +#ifdef CONFIG_PPC_BOOK3E
> +extern void tlb_flush_pgtable(struct mmu_gather *tlb, unsigned long address);
> +#else
> +#define tlb_flush_pgtable(tlb, address) do { } while(0)
static inline void tlb_flush_pgtable(s
On Sat, 2009-06-27 at 15:30 +1000, Paul Mackerras wrote:
> This provides a mechanism to allow the perf_counters code to access
> user memory in a PMU interrupt routine on a 64-bit kernel. Such an
> access can cause a SLB miss interrupt and/or a MMU hash table miss
> interrupt.
>
> An SLB miss int
Hi Ben,
On Thu, 23 Jul 2009 15:59:44 +1000 Benjamin Herrenschmidt
wrote:
>
> Index: linux-work/arch/powerpc/mm/mmu_context_hash64.c
> ===
> --- linux-work.orig/arch/powerpc/mm/mmu_context_hash64.c 2009-07-22
> 16:24:43.000
Here is a series of patches that implement some basic support
for 64-bit Book3E processors that comply to architecture 2.06.
There is no specific processor announced yet. The patches make
some shortcut which means they currently rely on an implementation
that supports MMU v2 with support for the "
This contains all the bits that didn't fit in previous patches :-) This
includes the actual exception handlers assembly, the changes to the
kernel entry, other misc bits and wiring it all up in Kconfig.
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/Kconfig |2
ar
The base TLB support didn't include support for SPARSEMEM_VMEMMAP, though
we did carve out some virtual space for it, the necessary support code
wasn't there. This implements it by using 16M pages for now, though the
page size could easily be changed at runtime if necessary.
Signed-off-by: Benjami
This adds the TLB miss handler assembly, the low level TLB flush routines
along with the necessary hook for dealing with our virtual page tables
or indirect TLB entries that need to be flushes when PTE pages are freed.
There is currently no support for hugetlbfs
Signed-off-by: Benjamin Herrenschm
The definition for the global structure mmu_gathers, used by generic code,
is currently defined in multiple places not including anything used by
64-bit Book3E. This changes it by moving to one place common to all
processors.
Signed-off-by: Benjamin Herrenschmidt
arch/powerpc/mm/init_32.c|
This adds various fields in the PACA that are for use specifically
by Book3E processors, such as exception save areas, current pgd
pointer, special exceptions kernel stacks etc...
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/include/asm/paca.h | 23 ---
arch/po
This adds various definitions and macros used by the exception and TLB
miss handling on 64-bit BookE
It also adds the definitions of the SPRGs used for various exception types
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/include/asm/exception-64e.h | 200
This adds the PTE and pgtable format definitions, along with changes
to the kernel memory map and other definitions related to implementing
support for 64-bit Book3E. This also shields some asm-offset bits that
are currently only relevant on 32-bit
Signed-off-by: Benjamin Herrenschmidt
---
arch
This adds various SPRs defined on 64-bit BookE, along with changes
to the definition of the base MSR values to add the values needed
for 64-bit Book3E.
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/include/asm/reg.h | 10 +++---
arch/powerpc/include/asm/reg_booke.h | 35 +
64-bit BookE will use that hook to maintain the virtually linear
page tables or the indirect entries in the TLB when using the
HW loader.
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/include/asm/pgalloc.h | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
--- linux
Those definitions are currently declared extern in the .c file where
they are used, move them to a header file instead.
Signed-off-by: Benjamin Herrenschmidt
--
arch/powerpc/include/asm/smp.h |5 +
arch/powerpc/kernel/setup_64.c |3 ---
2 files changed, 5 insertions(+), 3 deletions(
Currently, a single ifdef covers SLB related bits and more generic ppc64
related bits, split this in two separate ifdef's since 64-bit BookE will
need one but not the other.
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/kernel/process.c |2 ++
1 file changed, 2 insertions(+)
--- l
Our 64-bit hash context handling has no init function, but 64-bit Book3E
will use the common mmu_context_nohash.c code which does, so define an
empty inline mmu_context_init() for 64-bit server and call it from
our 64-bit setup_arch()
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/inclu
We need to pass down whether the page is direct or indirect and we'll
need to pass the page size to _tlbil_va and _tlbivax_bcast
We also add a new low level _tlbil_pid_noind() which does a TLB flush
by PID but avoids flushing indirect entries if possible
This implements those new prototypes but d
The way I intend to use tophys/tovirt on 64-bit BookE is different
from the "trick" that we currently play for 32-bit BookE so change
the condition of definition of these macros to make it so.
Also, make sure we only use rfid and mtmsrd instead of rfi and mtmsr
for 64-bit server processors, not al
This adds some code to do early ioremap's using page tables instead of
bolting entries in the hash table. This will be used by the upcoming
64-bits BookE port.
The patch also changes the test for early vs. late ioremap to use
slab_is_available() instead of our old hackish mem_init_done.
Signed-of
This adds various additional bit definitions for various MMU related
SPRs used on Book3E.
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/include/asm/mmu-book3e.h | 168 --
1 file changed, 119 insertions(+), 49 deletions(-)
--- linux-work.orig/arch/power
This adds the opcode definitions to ppc-opcode.h for the two instructions
tlbivax and tlbsrx. as defined by Book3E 2.06
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/include/asm/ppc-opcode.h |6 ++
1 file changed, 6 insertions(+)
--- linux-work.orig/arch/powerpc/include/asm/pp
The current "no hash" MMU context management code is written with
the assumption that one CPU == one TLB. This is not the case on
implementations that support HW multithreading, where several
linux CPUs can share the same TLB.
This adds some basic support for this to our context management
and our
enter_prom() used to save and restore registers such as CTR, XER etc..
which are volatile, or SRR0,1... which we don't care about. This
removes a bunch of useless code and while at it turns an mtmsrd into
an MTMSRD macro which will be useful to Book3E.
Signed-off-by: Benjamin Herrenschmidt
---
A misplaced #endif causes more definitions than intended to be
protected by #ifndef __ASSEMBLY__. This breaks upcoming 64-bit
BookE support patch when using 64k pages.
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/include/asm/pgtable-ppc64-64k.h |4 +---
1 file changed, 1 insertion
On Wed, 2009-07-22 at 16:41 -0700, Mike Mason wrote:
> Michael Ellerman wrote:
> > On Thu, 2009-07-16 at 09:33 -0700, Mike Mason wrote:
> >> Michael Ellerman wrote:
> >>> On Wed, 2009-07-15 at 14:43 -0700, Mike Mason wrote:
> This patch increments the device_node reference counter when an EEH
On Jul 22, 2009, at 11:32 AM, srikanth krishnakar wrote:
On Wed, Jul 22, 2009 at 9:14 PM, Kumar Gala
wrote:
On Jul 22, 2009, at 10:38 AM, srikanth krishnakar wrote:
On Wed, Jul 22, 2009 at 8:52 PM, Kumar Gala
wrote:
I'm not seeing any BUG* in traps.c @ line 904.
On Jul 21, 2009,
On Jul 22, 2009, at 7:53 PM, Benjamin Herrenschmidt wrote:
On Wed, 2009-07-22 at 09:31 -0700, Linus Torvalds wrote:
CC'ing Linus here. How do you want to proceed with that merge ?
(IE. so
far nobody objected to the patch itself)
Maybe you can put it as a separate branch in -next, and have
On Wed, 2009-07-22 at 09:31 -0700, Linus Torvalds wrote:
> > CC'ing Linus here. How do you want to proceed with that merge ? (IE. so
> > far nobody objected to the patch itself)
>
> Maybe you can put it as a separate branch in -next, and have it merged
> before the stuff that depends on it, and t
From: Mark Ware
Date: Thu, 23 Jul 2009 09:40:10 +0930
>
> The patch is actually attached this time. (I hope - did I mention my dislike
> for this webmail interface?)
No it isn't!
And anyways you have to properly provide the full commit message
and signoffs when you resubmit patches. You can
From: Mark Ware
Date: Thu, 23 Jul 2009 09:02:07 +0900
> Patch is attached, hopefully with correct MIME type - this webmail
> client is worse than Outlook.
Where is it attached? :-/
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On Thu 23/07/09 2:10 AM , David Miller da...@davemloft.net sent:
> Your email client has massively corrupted this patch, I even tried
> to fix it up but it's so bad that I just gave up half-way through.
>
> Please use an attachment or whatever is necessary to get this
> patch submitted cleanly a
On Thu 23/07/09 2:10 AM , David Miller da...@davemloft.net sent:
> Your email client has massively corrupted this patch, I even tried
> to fix it up but it's so bad that I just gave up half-way through.
>
> Please use an attachment or whatever is necessary to get this
> patch submitted cleanly a
Michael Ellerman wrote:
On Thu, 2009-07-16 at 09:33 -0700, Mike Mason wrote:
Michael Ellerman wrote:
On Wed, 2009-07-15 at 14:43 -0700, Mike Mason wrote:
This patch increments the device_node reference counter when an EEH
error occurs and decrements the counter when the event has been
handled.
On Wed, Jul 22, 2009 at 9:14 PM, Kumar Gala wrote:
>
> On Jul 22, 2009, at 10:38 AM, srikanth krishnakar wrote:
>
>
>>
>> On Wed, Jul 22, 2009 at 8:52 PM, Kumar Gala
>> wrote:
>> I'm not seeing any BUG* in traps.c @ line 904.
>>
>>
>> On Jul 21, 2009, at 4:33 AM, srikanth krishnakar wrote:
>>
>>
On Wed, Jul 22, 2009 at 8:52 PM, Kumar Gala wrote:
> I'm not seeing any BUG* in traps.c @ line 904.
>
> On Jul 21, 2009, at 4:33 AM, srikanth krishnakar wrote:
>
> The LTP test case msgctl10.c fails on linux-2.6.29.6 for PowerPC
>> architecture (ppc440)
>>
>>
>> msgctl101 B[ cut
dtc was moved in 9fffb55f66127b52c937ede5196ebfa0c0d50bce from
arch/powerpc/boot/ to scripts/dtc/
This patch updates the wrapper script to point to the new location of dtc.
Signed-off-by: Lucian Adrian Grijincu
---
arch/powerpc/boot/wrapper |3 ++-
1 files changed, 2 insertions(+), 1 dele
On Tue, Jul 21, 2009 at 10:47:39PM +1000, Benjamin Herrenschmidt wrote:
> On Tue, 2009-07-21 at 14:00 +0200, Gabriel Paubert wrote:
> > Well, I got one recently here in Spain. Shipping charges are fairly
> > large (it's not exactly a light and compact machine). But the current
> > dollar exchange
From: Mark Ware
Date: Wed, 22 Jul 2009 08:24:15 +1000
> Changes to the fs_enet driver
> (aa73832c5a80d6c52c69b18af858d88fa595dd3c) cause kernel crashes when
> using the mdio-ofgpio driver.
>
> This patch replicates similar changes made to the fs_enet mii-bitbang
> drivers. It has been tested on
On Mon, 20 Jul 2009, Benjamin Herrenschmidt wrote:
> On Wed, 2009-07-15 at 15:56 +0200, Nick Piggin wrote:
> > > I would like to merge the new support that depends on this in 2.6.32,
> > > so unless there's major objections, I'd like this to go in early during
> > > the merge window. We can sort
From: Grant Likely
Date: Sat, 18 Jul 2009 12:37:34 -0600
> Awesome. Dave, can you please pick up this series?
Sure thing.
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On Jul 22, 2009, at 10:38 AM, srikanth krishnakar wrote:
On Wed, Jul 22, 2009 at 8:52 PM, Kumar Gala
wrote:
I'm not seeing any BUG* in traps.c @ line 904.
On Jul 21, 2009, at 4:33 AM, srikanth krishnakar wrote:
The LTP test case msgctl10.c fails on linux-2.6.29.6 for PowerPC
architec
I'm not seeing any BUG* in traps.c @ line 904.
On Jul 21, 2009, at 4:33 AM, srikanth krishnakar wrote:
The LTP test case msgctl10.c fails on linux-2.6.29.6 for PowerPC
architecture (ppc440)
msgctl101 B[ cut here ]
kernel BUG at arch/powerpc/kernel/traps.c:904!
O
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