Hi, Kumar,
I tried to update the patch based on the latest kernel tree
(2.6.32-rc6), there are some problems:
1) the P2020DS board has supported SDHC using DMA, and the latest kernel
tree has included the related code, it doesn't need most of the patches
I posted before.
2) I compiled the image,
Hi Grant:
Thanks a lot for pushing the stuff to 'test'.
up patch 3. BUT, you're on my shit list. Patch 2 in your series
conflicts with this patch. I had to fix it up by hand. This patch
I'm sorry for that confusion! I actually merged this patch into
Hi Wolfram:
up patch 3. BUT, you're on my shit list. Patch 2 in your series
Huh, are you in a bad mood today? IMHO he addressed some valid issues; and
Actually, Grant is right here, as I confused two things, see my other reply...
Thanks, Albrecht.
Jetzt NEU: Do it youself E-Cards bei
);
BUG_ON(mm-nr_ptes (FIRST_USER_ADDRESS+PMD_SIZE-1)PMD_SHIFT);
}
Here is the information collected with today's next.
(2.6.32-rc7-20091113)
[ cut here ]
kernel BUG at mm/mmap.c:2139!
cpu 0x3: Vector: 700 (Program Check) at [c000fae1b7e0]
pc: c0150e88
Hi Grand,
here are the V2 of my patchset for mpc52xx_spi. Besides Wolframs suggestions I
also added some more fixes. Details of changes can be checked in the patch
header. Please do consider to apply the patches. The patch 1/2 e.g. fix bugs,
which prevent the driver to work in some cases, as
V2 changes:
* remove CS_HIGH mode
Signed-off-by: Luotao Fu l...@pengutronix.de
Acked-by: Wolfram Sang w.s...@pengutronix.de
---
drivers/spi/mpc52xx_spi.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/drivers/spi/mpc52xx_spi.c b/drivers/spi/mpc52xx_spi.c
index
Before reading status register to check MODF failure, we have to clear it
first since the MODF flag will be set after initializing the spi master,
if the hardware comes up with a low SS. The processor datasheet reads:
Mode Fault flag -- bit sets if SS input goes low while SPI is configured as a
This one enables the mpc52xx_spi driver for usage of user defined gpio lines
as chipselect. This way we can control some more spi devices than only one
V2 Changes:
* preinitialize the gpio as output in probe function and call gpio_set_value in
the chip select function instead of calling
On Fri, Nov 13, 2009 at 11:41:17AM +0100, Luotao Fu wrote:
This one enables the mpc52xx_spi driver for usage of user defined gpio lines
as chipselect. This way we can control some more spi devices than only one
V2 Changes:
* preinitialize the gpio as output in probe function and call
This patch splits the xilinx_spi driver into a generic part and a
OF driver part.
The reason for this is to later add in a platform driver as well.
Tested-by: John Linn john.l...@xilinx.com
Signed-off-by: Richard Röjfors richard.rojf...@mocean-labs.com
---
diff --git a/drivers/spi/Kconfig
This patch changes the out_(be)(8|16|32) and in_(be)(8|16|32) calls to 32 bits
ioread/iowrite.
The read and write function are attached to the internal struct as callbacks,
callback
is selected depending on endianess.
This will also build on platforms not supporting the in/out calls for
Hi,
To follow is a series of patches against the xilinx_spi driver.
The patchset is against 2.6.32-rc6
The patchset addresses several problems in the current driver:
* It's PPC only (OF and uses PPC specific memory operations)
* Only supporting big endian writes
* Supports only 8bit SPI,
This patch adds in support for the DS570 IP.
It's register compatible with the DS464, but adds support for 8/16/32 SPI.
The 8/16/32 support is added by attaching callbacks reading/writing the
proper amount of data. To indicate to the driver which amount of bits
to use a new field is introduced
This patch adds in a platform device driver using the xilinx_spi common module.
Tested-by: John Linn john.l...@xilinx.com
Signed-off-by: Richard Röjfors richard.rojf...@mocean-labs.com
---
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 35fb1e2..b0cfc98 100644
---
The following changes since commit 0526484aa345adbf790d1201a6f5d09be0a648a3:
Benjamin Herrenschmidt (1):
Merge commit 'origin/master' into next
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git next
Anton Vorontsov (18):
Taken from socketcan-svn, fixed remaining todos, cleaned up, tested with a
phyCORE-MPC5200B-IO and a custom board.
Signed-off-by: Wolfram Sang w.s...@pengutronix.de
Cc: Wolfgang Grandegger w...@grandegger.com
Cc: Grant Likely grant.lik...@secretlab.ca
Cc: David Miller da...@davemloft.net
---
On Fri, Nov 13, 2009 at 9:14 AM, Wolfram Sang w.s...@pengutronix.de wrote:
Taken from socketcan-svn, fixed remaining todos, cleaned up, tested with a
phyCORE-MPC5200B-IO and a custom board.
Signed-off-by: Wolfram Sang w.s...@pengutronix.de
Cc: Wolfgang Grandegger w...@grandegger.com
Cc:
On Fri, Nov 13, 2009 at 4:10 AM, Wolfram Sang w.s...@pengutronix.de wrote:
On Fri, Nov 13, 2009 at 11:41:17AM +0100, Luotao Fu wrote:
This one enables the mpc52xx_spi driver for usage of user defined gpio lines
as chipselect. This way we can control some more spi devices than only one
V2
On Fri, Nov 13, 2009 at 5:28 AM, Richard Röjfors
richard.rojf...@mocean-labs.com wrote:
Hi,
To follow is a series of patches against the xilinx_spi driver.
The patchset is against 2.6.32-rc6
The patchset addresses several problems in the current driver:
* It's PPC only (OF and uses PPC
On Fri, Nov 13, 2009 at 3:41 AM, Luotao Fu l...@pengutronix.de wrote:
Hi Grand,
here are the V2 of my patchset for mpc52xx_spi. Besides Wolframs suggestions I
also added some more fixes. Details of changes can be checked in the patch
header. Please do consider to apply the patches. The patch
I wrote a custom driver for an MPC8313 based board. Everything seems to
have been working for a long time, but now one of my IOCTL functions seems
to be having a problem. I'm getting a Bus error reported by my
application and also a kernel Oops. Here's what the kernel is reporting.
Oops:
Joakim Tjernlund wrote:
Anyhow, lets start simple and just do the pinned ITLB so the
new TLB code can be applied. Can you confirm this works for you?
It works (after changing #ifdef 1 to #if 1).
-Scott
___
Linuxppc-dev mailing list
Ron Madrid wrote:
I wrote a custom driver for an MPC8313 based board. Everything seems to
have been working for a long time, but now one of my IOCTL functions seems
to be having a problem. I'm getting a Bus error reported by my
application and also a kernel Oops. Here's what the kernel is
--- On Fri, 11/13/09, Scott Wood scottw...@freescale.com wrote:
From: Scott Wood scottw...@freescale.com
Subject: Re: Bus Error on MPC8313
To: Ron Madrid ron_mad...@sbcglobal.net
Cc: linuxppc-...@ozlabs.org
Date: Friday, November 13, 2009, 11:33 AM
Ron Madrid wrote:
I wrote a custom
Ron Madrid wrote:
--- On Fri, 11/13/09, Scott Wood scottw...@freescale.com wrote:
From: Scott Wood scottw...@freescale.com
Subject: Re: Bus Error on MPC8313
To: Ron Madrid ron_mad...@sbcglobal.net
Cc: linuxppc-...@ozlabs.org
Date: Friday, November 13, 2009, 11:33 AM
Ron Madrid wrote:
I wrote
-Original Message-
From: glik...@secretlab.ca [mailto:glik...@secretlab.ca] On Behalf Of Grant
Likely
Sent: Friday, November 13, 2009 11:30 AM
To: Richard Röjfors
Cc: spi-devel-gene...@lists.sourceforge.net; linuxppc-...@ozlabs.org; Andrew
Morton;
dbrown...@users.sourceforge.net;
--- On Fri, 11/13/09, Scott Wood scottw...@freescale.com wrote:
And when this
does happen in usually causes a lockup, so I haven't
been able to check the
status of any arbiter registers.
The system is up long enough to print an oops; you could
stick some output in the trap handler.
On Fri, Nov 13, 2009 at 12:59 PM, John Linn john.l...@xilinx.com wrote:
-Original Message-
From: glik...@secretlab.ca [mailto:glik...@secretlab.ca] On Behalf Of Grant
Likely
Sent: Friday, November 13, 2009 11:30 AM
To: Richard Röjfors
Cc: spi-devel-gene...@lists.sourceforge.net;
Ron Madrid wrote:
Are there any filesystems mounted on NAND? There are
some issues with transactions timing out if there's
contention with a long-running NAND operation.
Yes, a JFFS2. If that is the case, is there any sort of
workaround?
I've just posted some patches to linuxppc-dev and
We want error information even if the kernel hasn't been built for verbose
debugging.
Signed-off-by: Scott Wood scottw...@freescale.com
---
drivers/mtd/nand/fsl_elbc_nand.c | 13 -
1 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c
When a NAND operation is in progress, all other localbus operations
(including NOR flash) will have to wait for access to the bus. However, the
NAND operation may take longer to complete than the default timeout. Thus,
if NOR is accessed while a NAND operation is in progress, the NAND operation
Currently, the program and erase sequences do not wait for completion,
instead relying on a subsequent waitfunc() callback. However, this causes
the chipselect to be deasserted while the NAND chip is still asserting the
busy pin, which can corrupt activity on other chipselects.
This patch
Hello,
I have seen an intermittent problem in the driver:
drivers/ata/pata_mpc52xx.c
The intermittent error is that the bestcomm dma engine gets stuck. I
don't believe the driver itself is causing the dma error. However, I do
want to enhance the driver so that it can recover from the dma
From: Wolfram Sang w.s...@pengutronix.de
Date: Fri, 13 Nov 2009 17:14:52 +0100
Taken from socketcan-svn, fixed remaining todos, cleaned up, tested with a
phyCORE-MPC5200B-IO and a custom board.
Signed-off-by: Wolfram Sang w.s...@pengutronix.de
Applied.
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