Bug in drivers/serial/of_serial.c?

As of commit eedacbf0, drivers/serial/of_serial.c forces the serial core to recognize the xps-uart16550-2.00.b as an NS16550 (which had no FIFO). Prior to this commit, the kernel's auto-configuration logic would correctly recognize the UART as NS16550A (with 16-byte FIFO). The following patch

[PATCH/RFC] Booting Xilinx ML510 board using SystemACE

I am using locally the attached (hackish) patch; could someone propose a way to make it acceptable to mainline (or should I just keep this quiet)? diff --git a/arch/powerpc/platforms/44x/virtex.c b/arch/powerpc/platforms/44x/virtex.c index cf96cca..749a330 100644 ---

Re: [PATCH] net/can: add driver for mscan family mpc52xx_mscan

David Miller wrote: From: Wolfram Sang w.s...@pengutronix.de Date: Fri, 13 Nov 2009 17:14:52 +0100 Taken from socketcan-svn, fixed remaining todos, cleaned up, tested with a phyCORE-MPC5200B-IO and a custom board. Signed-off-by: Wolfram Sang w.s...@pengutronix.de Applied. Unfortunately

Re: [PATCH 04/10] 8xx: Always pin kernel instruction TLB

Dan Malek d...@embeddedalley.com wrote on 14/11/2009 19:08:43: On Nov 14, 2009, at 2:42 AM, Joakim Tjernlund wrote: . Avoid this by always pinning kernel instruction TLB space. You may as well map the data space, too, since you have reserved the entries. Take advantage of

[PATCH 00/10] Fix 8xx MMU/TLB

[I used the wrong branch, this will hopefully not conflict] This is hopfully the last iteration of the series. Rex Scott, please test and signoff. Changes since last version: - Added mandatory pinning of iTLB - Added DTLB Miss cleanup Joakim Tjernlund (10): 8xx: invalidate non present TLBs

[PATCH 01/10] 8xx: invalidate non present TLBs

8xx sometimes need to load a invalid/non-present TLBs in it DTLB asm handler. These must be invalidated separaly as linux mm don't. Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se --- arch/powerpc/mm/fault.c |8 +++- 1 files changed, 7 insertions(+), 1 deletions(-) diff

[PATCH 02/10] 8xx: Update TLB asm so it behaves as linux mm expects.

Update the TLB asm to make proper use of _PAGE_DIRY and _PAGE_ACCESSED. Get rid of _PAGE_HWWRITE too. Pros: - I/D TLB Miss never needs to write to the linux pte. - _PAGE_ACCESSED is only set on TLB Error fixing accounting - _PAGE_DIRTY is mapped to 0x100, the changed bit, and is set directly

[PATCH 03/10] 8xx: Tag DAR with 0x00f0 to catch buggy instructions.

dcbz, dcbf, dcbi, dcbst and icbi do not set DAR when they cause a DTLB Error. Dectect this by tagging DAR with 0x00f0 at every exception exit that modifies DAR. Test for DAR=0x00f0 in DataTLBError and bail to handle_page_fault(). Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se ---

[PATCH 04/10] 8xx: Always pin kernel instruction TLB

Various kernel asm modifies SRR0/SRR1 just before executing a rfi. If such code crosses a page boundary you risk a TLB miss which will clobber SRR0/SRR1. Avoid this by always pinning kernel instruction TLB space. Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se ---

[PATCH 05/10] 8xx: Fixup DAR from buggy dcbX instructions.

This is an assembler version to fixup DAR not being set by dcbX, icbi instructions. There are two versions, one uses selfmodifing code, the other uses a jump table but is much bigger(default). Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se --- arch/powerpc/kernel/head_8xx.S | 147

[PATCH 06/10] 8xx: Add missing Guarded setting in DTLB Error.

only DTLB Miss did set this bit, DTLB Error needs too otherwise the setting is lost when the page becomes dirty. Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se --- arch/powerpc/kernel/head_8xx.S | 13 ++--- 1 files changed, 10 insertions(+), 3 deletions(-) diff --git

[PATCH 07/10] 8xx: Restore _PAGE_WRITETHRU

8xx has not had WRITETHRU due to lack of bits in the pte. After the recent rewrite of the 8xx TLB code, there are two bits left. Use one of them to WRITETHRU. Perhaps use the last SW bit to PAGE_SPECIAL or PAGE_FILE? Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se ---

[PATCH 08/10] 8xx: start using dcbX instructions in various copy routines

Now that 8xx can fixup dcbX instructions, start using them where possible like every other PowerPc arch do. Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se --- arch/powerpc/kernel/misc_32.S | 18 -- arch/powerpc/lib/copy_32.S| 24 2

[PATCH 09/10] 8xx: Remove DIRTY pte handling in DTLB Error.

There is no need to do set the DIRTY bit directly in DTLB Error. Trap to do_page_fault() and let the generic MM code do the work. Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se --- arch/powerpc/kernel/head_8xx.S | 96 1 files changed, 0

[PATCH 10/10] 8xx: DTLB Miss cleanup

Use symbolic constant for PRESENT and avoid branching. Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se --- arch/powerpc/kernel/head_8xx.S | 17 +++-- 1 files changed, 11 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/kernel/head_8xx.S

[Q/RFC] mpc52xx gpt api

Hi all, I tried to use a '5200B internal timer for a very simple task - as pwm to make a led blink, but apparently the current gpt implementation from Grant's tree does only support internal (cpu timer) modes which do not use the timer io pin. The first hurdle was to actually get the timer

[PATCH 1/1] ata/sata_sil24: MSI support, disabled by default

The following patch adds MSI support. Some platforms may have broken MSI, so those are defaulted to use legacy PCI interrupts. Signed-off-by: Vivek Mahajan vivek.maha...@freescale.com --- drivers/ata/sata_sil24.c |9 + 1 files changed, 9 insertions(+), 0 deletions(-) diff --git