From: Liu Shuo
Flash_erase -j should fill discrete freeoob areas with required bytes
of JFFS2 cleanmarker in jffs2_check_nand_cleanmarker(). Not just fill
the first freeoob area.
Signed-off-by: Liu Shuo
Signed-off-by: Li Yang
---
flash_erase.c | 41 +++--
Vineeth wrote:
> Thanks for the reply.
>
> We were referring kuroboxHG.dts which uses Sandpoint architecture; which is
> almost same as ours.
>
> 1. one doubt in kuroboxHG is the ranges property in SOC node says EUMB is at
> 0xFC00_; and as per the datasheet of mpc107, the open pic address wi
>-Original Message-
>From: Liu Shuo-B35362
>Sent: Tuesday, July 12, 2011 12:49 PM
>To: dw...@infradead.org
>Cc: linux-...@lists.infradead.org; linuxppc-...@ozlabs.org; Liu Shuo-
>B35362; Li Yang-R58472
>Subject: [PATCH v2] mtd/nand : workaround for Freescale FCM to support
>large-page Nand
On Wed, 2011-08-03 at 12:04 +1000, David Gibson wrote:
> On Tue, Aug 02, 2011 at 12:35:19PM -0600, Alex Williamson wrote:
> > On Tue, 2011-08-02 at 12:14 -0600, Alex Williamson wrote:
> > > On Tue, 2011-08-02 at 18:28 +1000, David Gibson wrote:
> > > > On Sat, Jul 30, 2011 at 12:20:08PM -0600, Alex
On Tue, Aug 02, 2011 at 04:47:08PM +0200, Alexander Graf wrote:
> > int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, struct kvm_interrupt
> > *irq)
> > {
> >-if (irq->irq == KVM_INTERRUPT_UNSET)
> >+if (irq->irq == KVM_INTERRUPT_UNSET) {
> > kvmppc_core_dequeue_external(v
On Tue, Aug 02, 2011 at 12:35:19PM -0600, Alex Williamson wrote:
> On Tue, 2011-08-02 at 12:14 -0600, Alex Williamson wrote:
> > On Tue, 2011-08-02 at 18:28 +1000, David Gibson wrote:
> > > On Sat, Jul 30, 2011 at 12:20:08PM -0600, Alex Williamson wrote:
> > > > On Sat, 2011-07-30 at 09:58 +1000, B
On Tue, 2011-08-02 at 17:29 -0400, Konrad Rzeszutek Wilk wrote:
> On Tue, Aug 02, 2011 at 09:34:58AM -0600, Alex Williamson wrote:
> > On Tue, 2011-08-02 at 22:58 +1000, Benjamin Herrenschmidt wrote:
> > >
> > > Don't worry, it took me a while to get my head around the HW :-) SR-IOV
> > > VFs will
Sent from my HTC Touch HD
-Original Message-
From: linuxppc-dev-bounces+dm=mdtech...@lists.ozlabs.org
Sent: 01 августа 2011 23:58
To: Geert Uytterhoeven
Cc: Geoff Levand ; cbe-oss-...@lists.ozlabs.org
; Hector Martin ;
linuxppc-dev@lists.ozlabs.org
Subject: Re: [Cbe-oss-dev] [PATCH
On Tue, Aug 02, 2011 at 09:34:58AM -0600, Alex Williamson wrote:
> On Tue, 2011-08-02 at 22:58 +1000, Benjamin Herrenschmidt wrote:
> >
> > Don't worry, it took me a while to get my head around the HW :-) SR-IOV
> > VFs will generally not have limitations like that no, but on the other
> > hand, t
Adds support for External Proxy (a.k.a. CoreInt) interrupts on 64-bit
kernels. External Proxy combines interrupt delivery and
acknowledgement, so simply returning from the interrupt without EOI
or other action will not result in the interrupt being reasserted.
When an external interrupt is deferr
On Tue, 2011-08-02 at 12:14 -0600, Alex Williamson wrote:
> On Tue, 2011-08-02 at 18:28 +1000, David Gibson wrote:
> > On Sat, Jul 30, 2011 at 12:20:08PM -0600, Alex Williamson wrote:
> > > On Sat, 2011-07-30 at 09:58 +1000, Benjamin Herrenschmidt wrote:
> > [snip]
> > > On x86, the USB controllers
On Tue, 2011-08-02 at 18:28 +1000, David Gibson wrote:
> On Sat, Jul 30, 2011 at 12:20:08PM -0600, Alex Williamson wrote:
> > On Sat, 2011-07-30 at 09:58 +1000, Benjamin Herrenschmidt wrote:
> [snip]
> > On x86, the USB controllers don't typically live behind a PCIe-to-PCI
> > bridge, so don't suff
On Tue, 2011-08-02 at 22:58 +1000, Benjamin Herrenschmidt wrote:
>
> Don't worry, it took me a while to get my head around the HW :-) SR-IOV
> VFs will generally not have limitations like that no, but on the other
> hand, they -will- still require 1 VF = 1 group, ie, you won't be able to
> take a
On 07/23/2011 09:42 AM, Paul Mackerras wrote:
With a KVM guest operating in SMT4 mode (i.e. 4 hardware threads per
core), whenever a CPU goes idle, we have to pull all the other
hardware threads in the core out of the guest, because the H_CEDE
hcall is handled in the kernel. This is inefficient.
On Tue, 2011-08-02 at 11:27 +1000, Benjamin Herrenschmidt wrote:
> It's a shared address space. With a basic configuration on p7ioc for
> example we have MMIO going from 3G to 4G (PCI side addresses). BARs
> contain the normal PCI address there. But that 1G is divided in 128
> segments of equal siz
On 08/02/2011 03:58 PM, Benjamin Herrenschmidt wrote:
> >
> > What you mean 2-level is two passes through two trees (ie 6 or 8 levels
> > right ?).
>
> (16 or 25)
25 levels ? You mean 25 loads to get to a translation ? And you get any
kind of performance out of that ? :-)
Aggressive par
On Tue, 2011-08-02 at 12:12 +0300, Avi Kivity wrote:
> On 08/02/2011 04:27 AM, Benjamin Herrenschmidt wrote:
> > >
> > > I have a feeling you'll be getting the same capabilities sooner or
> > > later, or you won't be able to make use of S/R IOV VFs.
> >
> > I'm not sure why you mean. We can do SR
On 07/23/2011 09:41 AM, Paul Mackerras wrote:
This makes arch/powerpc/kvm/book3s_rmhandlers.S and
arch/powerpc/kvm/book3s_hv_rmhandlers.S be assembled as
separate compilation units rather than having them #included in
arch/powerpc/kernel/exceptions-64s.S. We no longer have any
conditional branch
Hi,
On 07/31/2011 04:59 PM, Tabi Timur-B04825 wrote:
Felix Radensky wrote:
What happens when I load my driver is single execution of interrupt
handler
followed by system freeze. Even if I call disable_irq() in interrupt
handler the
system still freezes.
I don't know anything
On Sat, Jul 30, 2011 at 12:20:08PM -0600, Alex Williamson wrote:
> On Sat, 2011-07-30 at 09:58 +1000, Benjamin Herrenschmidt wrote:
[snip]
> On x86, the USB controllers don't typically live behind a PCIe-to-PCI
> bridge, so don't suffer the source identifier problem, but they do often
> share an in
On Wed, Jul 27, 2011 at 11:47:40AM +0200, Sven Eckelmann wrote:
For MIPS:
Acked-by: Ralf Baechle
Ralf
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Thanks for the reply.
We were referring kuroboxHG.dts which uses Sandpoint architecture; which is
almost same as ours.
1. one doubt in kuroboxHG is the ranges property in SOC node says EUMB is at
0xFC00_; and as per the datasheet of mpc107, the open pic address will
be EUMB_BASE + 0x4; bu
On 08/02/2011 04:27 AM, Benjamin Herrenschmidt wrote:
>
> I have a feeling you'll be getting the same capabilities sooner or
> later, or you won't be able to make use of S/R IOV VFs.
I'm not sure why you mean. We can do SR/IOV just fine (well, with some
limitations due to constraints with how
On 08/01/2011 11:27 PM, Alex Williamson wrote:
On Sun, 2011-07-31 at 17:09 +0300, Avi Kivity wrote:
> On 07/30/2011 02:58 AM, Benjamin Herrenschmidt wrote:
> > Due to our paravirt nature, we don't need to masquerade the MSI-X table
> > for example. At all. If the guest configures crap into i
Vineeth wrote:
> Hi,
>
> We are trying to port linux 2.6.38 on MPC7410 based board (This is a
> preparatory design by our customer)
>
> System architecture is as follows,
>
> MPC7410 <=> MPC107 <=> PCI_to_LOCAL(plx9052) <=> UART
MPCXXX should be compatible with TSIXXX. So you can refer to mpc7
Hi,
We are trying to port linux 2.6.38 on MPC7410 based board (This is a
preparatory design by our customer)
System architecture is as follows,
MPC7410 <=> MPC107 <=> PCI_to_LOCAL(plx9052) <=> UART
Previously we were using ppc architecture and we had some issues with
page_init() functions; whi
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