Introduce some common components that we can utilize to build up the
various PQ3/85xx device trees.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
arch/powerpc/boot/dts/fsl/pq3-dma-0.dtsi| 32 +++
arch/powerpc/boot/dts/fsl/pq3-duart-0.dtsi |8 ++
Create a P1020 SoC dts stub that can be included by a board that
utilizes the P1020 SoC. The board can amend any board specific
configuration or paramaters (like locaation of CCSRBAR, PCIe
controllers, I2C components, ethernet PHY information, etc.)
Signed-off-by: Kumar Gala
On Sat, Oct 15, 2011 at 3:38 AM, tma...@apm.com wrote:
From: Tirumala Marri tma...@apm.com
[...]
+/*
+ * These Macros represents the bit fields in the FIFO Size Registers
(HPTXFSIZ,
+ * GNPTXFSIZ, DPTXFSIZn). Read the register into the u32 element then
+ * read out the bits using the bit
On Fri, Oct 7, 2011 at 8:00 AM, tma...@apm.com wrote:
From: Tirumala Marri tma...@apm.com
[...]
+ * Do core a soft reset of the core. Be careful with this because it
+ * resets all the internal state machines of the core.
+ */
+static void dwc_otg_core_reset(struct core_if *core_if)
+{
On Sat, Oct 15, 2011 at 3:38 AM, tma...@apm.com wrote:
From: Tirumala Marri tma...@apm.com
[...]
Everything fine in this patch, except the defines of TX
regs(DWC_RX_FIFO_DEPTH_WR) has been
kept with RX.
Regards
Pratyush
___
Linuxppc-dev mailing
On Sat, Oct 15, 2011 at 3:39 AM, tma...@apm.com wrote:
From: Tirumala Marri tma...@apm.com
Implements functions to manage Queue Heads and Queue
Transfer Descriptors of DWC USB OTG Controller.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
On Sat, Oct 15, 2011 at 3:39 AM, tma...@apm.com wrote:
From: Tirumala Marri tma...@apm.com
The PCD is responsible for translating requests from the gadget driver
to appropriate actions on the DWC OTG controller.
[...]
+static int dwc_otg_pcd_ep_disable(struct usb_ep *_ep)
+{
+
On Sat, Oct 15, 2011 at 3:39 AM, tma...@apm.com wrote:
From: Tirumala Marri tma...@apm.com
[...]
+static int write_empty_tx_fifo(struct dwc_pcd *pcd, u32 epnum)
+{
+ struct core_if *core_if = GET_CORE_IF(pcd);
+ ulong regs;
+ u32 txstatus = 0;
+ struct pcd_ep
Hello Tirumala,
I have some coding style comments below.
On Sat, Oct 15, 2011 at 12:09 AM, tma...@apm.com wrote:
From: Tirumala Marri tma...@apm.com
Implements functions to manage Queue Heads and Queue
Transfer Descriptors of DWC USB OTG Controller.
Signed-off-by: Tirumala R Marri
On Thu, Oct 20, 2011 at 2:24 AM, Kumar Gala ga...@kernel.crashing.org wrote:
arch/powerpc/boot/dts/p1020soc.dtsi | 262
+++
All of the other dtsi files are of the format ___si.dtsi. Why does
this one use ___soc.dtsi?
--
Timur Tabi
Linux kernel developer at
Ok, your other patch makes more sense now.
On Thu, Oct 20, 2011 at 2:24 AM, Kumar Gala ga...@kernel.crashing.org wrote:
+++ b/arch/powerpc/boot/dts/fsl/pq3-duart-0.dtsi
@@ -0,0 +1,8 @@
+serial0 {
+ cell-index = 0;
+ device_type = serial;
+ compatible = ns16550;
+
On Oct 20, 2011, at 11:42 AM, Tabi Timur-B04825 wrote:
Ok, your other patch makes more sense now.
On Thu, Oct 20, 2011 at 2:24 AM, Kumar Gala ga...@kernel.crashing.org wrote:
+++ b/arch/powerpc/boot/dts/fsl/pq3-duart-0.dtsi
@@ -0,0 +1,8 @@
+serial0 {
+ cell-index = 0;
+
On Oct 20, 2011, at 11:28 AM, Tabi Timur-B04825 wrote:
On Thu, Oct 20, 2011 at 2:24 AM, Kumar Gala ga...@kernel.crashing.org wrote:
arch/powerpc/boot/dts/p1020soc.dtsi | 262
+++
All of the other dtsi files are of the format ___si.dtsi. Why does
this
Kumar Gala wrote:
How about we put all serial devices into one pq3-duart.dtsi file, and
let the parent dtsi file reference just the ones that it needs?
there isn't an option to do that w/dtc
What about making all the nodes disabled by default, and then the soc.dtsi
or si.dtsi file can
By comparing the BCM5481 registers modified in the -config_aneg()
method with the datasheet I have for the BCM5482, it appears that the
register writes are adjusting signal timing to work around a known
trace-length issue on the PCB.
Such hardware workarounds don't belong in the generic driver,
The name of the phy_start_aneg() function is very confusing, because
it also handles forced-mode (AUTONEG_DISABLE) links.
Rename the function to phy_start_link() and fix up all users.
Signed-off-by: Kyle Moffett kyle.d.moff...@boeing.com
---
Documentation/networking/phy.txt |2 +-
On Oct 20, 2011, at 4:05 PM, Timur Tabi wrote:
Kumar Gala wrote:
How about we put all serial devices into one pq3-duart.dtsi file, and
let the parent dtsi file reference just the ones that it needs?
there isn't an option to do that w/dtc
What about making all the nodes disabled by
On Sat, Oct 15, 2011 at 3:38 AM, tma...@apm.com wrote:
From: Tirumala Marri tma...@apm.com
Platform probing is in apmppc.c.
Most if this file is common for other platform too.
So, why not extract common part and put them here.
All the platform specific whether PPC or ARM or else
should move
Hi Tirumala,
I have reviwed all the patches.
Thanks for taking my most of the diffs over your v13.
There are few thing, which are really very important like,
AHB disable check, EP Disable/Stall (have commented about them in
respective patches). I am doubtful, that how does all of usbcv test cases
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