Hello Maintainers:
Please help check this patch whether is OK, when you have time.
Thanks.
On 05/21/2013 05:20 PM, Chen Gang wrote:
>
> When error occurs, need return the related error code to let upper
> caller know about it.
>
> ppc_md.nvram_size() can return the error code (e.g. core99_nvram
On Friday 21 June 2013 05:04 AM, Sebastian Andrzej Siewior wrote:
> On 06/21/2013 02:52 AM, Santosh Shilimkar wrote:
>> diff --git a/arch/microblaze/kernel/prom.c b/arch/microblaze/kernel/prom.c
>> index 0a2c68f..62e2e8f 100644
>> --- a/arch/microblaze/kernel/prom.c
>> +++ b/arch/microblaze/kernel/
On Fri, Jun 21, 2013 at 9:56 AM, Peter LaDow wrote:
> We are running into a case where we get memory corruption when an
> external PCI master writes to the processor. We are using an MPC8349
> with an external Intel 82540EP (an E1000) part. I've spent several
> weeks on the e1000 list trying to
Vineet, James,
On Friday 21 June 2013 04:23 AM, James Hogan wrote:
> On 21/06/13 05:39, Vineet Gupta wrote:
>> Hi Santosh,
>>
>> On 06/21/2013 06:22 AM, Santosh Shilimkar wrote:
>>> Cc: Vineet Gupta
>>> Cc: Russell King
>>> Cc: Catalin Marinas
>>> Cc: Will Deacon
>>> Cc: Mark Salter
>>> Cc: A
I'm posting this to the ppc-dev since I think the problem may be
specific to the PPC kernel.
We are running into a case where we get memory corruption when an
external PCI master writes to the processor. We are using an MPC8349
with an external Intel 82540EP (an E1000) part. I've spent several
w
On Mon, Jun 10, 2013 at 10:18:08AM -0700, Guenter Roeck wrote:
> Commit 37f02195b (powerpc/pci: fix PCI-e devices rescan issue on powerpc
> platform) fixes a problem with interrupt and DMA initialization on hot
> plugged devices. With this commit, interrupt and DMA initialization for
> hot plugged
The original MPIC MSI bank contains 8 registers, MPIC v4.3 MSI bank
contains 16 registers, and this patch adds NR_MSI_REG_MAX and
NR_MSI_IRQS_MAX to describe the maximum capability of MSI bank.
MPIC v4.3 provides MSIIR1 to index these 16 MSI registers. MSIIR1
uses different bits definition than MSI
For the latest platform T4 and B4, MPIC controller has been updated
to v4.3. This patch adds a new file to describe the latest MPIC.
The MSI blocks number is increased to four, the registers number
of each block is increased to sixteen. MSIIR1 has been added to
access these sixteen MSI registers.
Add compatible "fsl,mpic-msi-v4.3" for MPIC v4.3. MPIC v4.3 contains
MSIIR and MSIIR1. MSIIR supports 8 MSI registers and MSIIR1 supports
16 MSI registers, but uses different IBS and SRS shift. When using
MSIR1, the interrupt number is not consecutive. It is hard to use
'msi-available-ranges' to de
On 06/21/2013 02:52 AM, Santosh Shilimkar wrote:
> diff --git a/arch/microblaze/kernel/prom.c b/arch/microblaze/kernel/prom.c
> index 0a2c68f..62e2e8f 100644
> --- a/arch/microblaze/kernel/prom.c
> +++ b/arch/microblaze/kernel/prom.c
> @@ -136,8 +136,7 @@ void __init early_init_devtree(void *params
Enable PSTORE in pseries_defconfig
Signed-off-by: Aruna Balakrishnaiah
---
arch/powerpc/configs/pseries_defconfig |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/configs/pseries_defconfig
b/arch/powerpc/configs/pseries_defconfig
index c4dfbaf..9630a50 100644
--- a/arch/power
On 21/06/13 05:39, Vineet Gupta wrote:
> Hi Santosh,
>
> On 06/21/2013 06:22 AM, Santosh Shilimkar wrote:
>> Cc: Vineet Gupta
>> Cc: Russell King
>> Cc: Catalin Marinas
>> Cc: Will Deacon
>> Cc: Mark Salter
>> Cc: Aurelien Jacquiot
>> Cc: James Hogan
>> Cc: Michal Simek
>> Cc: Ralf Baechle
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