Finally I found the problem causing the sudden system reset :
our setup :
P2020<>PCI Bridge <=> FPGA
The reset occurs when we allocating skb and giving the Fpga dma addr of
skb->data of this skb and when the FPGA tries to reach this address we are
having a hardware reset.
To fixed it w
发件人: Wood Scott-B07421
发送时间: 2014年1月8日 8:21
收件人: Tang Yuantian-B29983
抄送: ga...@kernel.crashing.org; mark.rutl...@arm.com;
devicet...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org
主题: Re: [v7] clk: corenet: Adds the clock binding
On Wed, Nov 20, 2013 at
On Wed, Jan 08, 2014 at 08:53:56AM +, Yuantian Tang wrote:
>
>
> 发件人: Wood Scott-B07421
> 发送时间: 2014年1月8日 8:21
> 收件人: Tang Yuantian-B29983
> 抄送: ga...@kernel.crashing.org; mark.rutl...@arm.com;
> devicet...@vger.kernel.org; linuxppc-dev@lists.ozlabs.or
Michael Ellerman writes:
> On Mon, 2013-12-30 at 15:31 +0100, Andreas Schwab wrote:
>> GCC 4.8 now generates out-of-line vr save/restore functions when
>> optimizing for size. They are needed for the raid6 altivec support.
>
> It looks like they're identical for 32 & 64-bit ?
They use different
Hi Andi,
> > Thoughts? It seems like we could hit a similar situation if a
> > machine is balanced but we run out of memory on a single node.
>
> Yes I agree, but your patch doesn't seem to attempt to handle this?
It doesn't. I was hoping someone with more mm knowledge than I could
suggest a li
Hi David,
> Why not just delete the entire test?
> Presumably some time a little earlier no local memory was available.
> Even if there is some available now, it is very likely that some won't
> be available again in the near future.
I agree, the current behaviour seems strange but it has been a
Hi Wanpeng,
> >+if (node_spanned_pages(node)) {
>
> s/node_spanned_pages/node_present_pages
Thanks, I hadn't come across node_present_pages() before.
Anton
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> -Original Message-
> From: kvm-ppc-ow...@vger.kernel.org [mailto:kvm-ppc-
> ow...@vger.kernel.org] On Behalf Of Alexander Graf
> Sent: Monday, December 09, 2013 5:02 PM
> To: "; " "@suse.de
> Cc: k...@vger.kernel.org mailing list
> Subject: [PATCH] KVM: PPC: Add devname:kvm aliases for mo
[ dropping devicetree from the Cc: list ]
[ what is the semantics of DMA_PRIVATE capability flag?
is documentation available beyond the initial commit message?
need individual channels be handled instead of controllers? ]
On Sat, Jan 04, 2014 at 00:54 +0400, Alexander Popov wrote:
>
> Hello
On Wed, Jan 08, 2014 at 03:18:26PM +1100, Benjamin Herrenschmidt wrote:
> On Wed, 2014-01-08 at 15:09 +1100, Michael Ellerman wrote:
> > > Of course, main worry is that this is just hiding some latent NULL
> > deref in
> > > the kernel now... :-/
> >
> > Wow, that would have to come close to winni
On Wed, 2014-01-08 at 09:30 +, Mark Rutland wrote:
> On Wed, Jan 08, 2014 at 08:53:56AM +, Yuantian Tang wrote:
> >
> >
> > 发件人: Wood Scott-B07421
> > 发送时间: 2014年1月8日 8:21
> > 收件人: Tang Yuantian-B29983
> > 抄送: ga...@kernel.crashing.org; mark.rutl...
Scott Wood wrote on 01/08/2014 10:51:10 AM:
> From: Scott Wood
> To: Stephen N Chivers/AUS/CSC@CSC
> Cc: ,
> Date: 01/08/2014 10:51 AM
> Subject: Re: [PATCH v5 1/1] powerpc/embedded6xx: Add support for
> Motorola/Emerson MVME5100
>
> On Mon, 2014-01-06 at 12:23 +1100, Stephen Chivers wrote:
>
On Wed, Jan 08, 2014 at 07:26:06PM +, Sudeep Holla wrote:
> From: Sudeep Holla
>
> This patch adds initial support for providing processor cache information
> to userspace through sysfs interface. This is based on x86 implementation
> and hence the interface is intended to be fully compatible
On Wed, Jan 08, 2014 at 07:26:06PM +, Sudeep Holla wrote:
> From: Sudeep Holla
>
> This patch adds initial support for providing processor cache information
> to userspace through sysfs interface. This is based on x86 implementation
> and hence the interface is intended to be fully compatible
On Wed, Jan 08, 2014 at 07:26:06PM +, Sudeep Holla wrote:
> From: Sudeep Holla
> +#define define_one_ro(_name) \
> +static struct cache_attr _name = \
> + __ATTR(_name, 0444, show_##_name, NULL)
In the future, we do have __ATTR_RO(), which should be used instead.
You should never use __AT
On Wed, Jan 08, 2014 at 07:26:07PM +, Sudeep Holla wrote:
> +#if __LINUX_ARM_ARCH__ < 7 /* pre ARMv7 */
> +
> +#define MAX_CACHE_LEVEL 1 /* Only 1 level supported */
> +#define CTR_CTYPE_SHIFT 24
> +#define CTR_CTYPE_MASK (1 << CTR_CTYPE_SHIFT)
> +
On Wed, 2014-01-08 at 00:24 -0800, ravich wrote:
> Finally I found the problem causing the sudden system reset :
>
> our setup :
>
> P2020<>PCI Bridge <=> FPGA
>
> The reset occurs when we allocating skb and giving the Fpga dma addr of
> skb->data of this skb and when the FPGA tries to r
On Wed, 2014-01-08 at 10:42 +0800, Kevin Hao wrote:
> On Tue, Jan 07, 2014 at 05:46:04PM -0600, Scott Wood wrote:
> > On Sat, 2014-01-04 at 14:34 +0800, Kevin Hao wrote:
> > > > I'm having a hard time following the logic here. What is PAGE_OFFSET -
> > > > offset supposed to be? Why would we map
On Wed, 2014-01-08 at 13:01 +0800, Minghuan Lian wrote:
> PowerPC uses structure pci_controller to describe PCI controller,
> but ARM uses structure pci_sys_data. In order to support PowerPC
> and ARM simultaneously, the patch adds a structure fsl_pci that
> contains most of the members of the pci_
Commit 446f6d06fab0b49c61887ecbe8286d6aaa796637 ("powerpc/mpic: Properly
set default triggers") breaks the mpc7447_hpc_defconfig as follows:
CC arch/powerpc/sysdev/mpic.o
arch/powerpc/sysdev/mpic.c: In function 'mpic_set_irq_type':
arch/powerpc/sysdev/mpic.c:886:9: error: case label does no
On Wed, Jan 08, 2014 at 10:42:35AM +0800, Kevin Hao wrote:
> On Tue, Jan 07, 2014 at 05:46:04PM -0600, Scott Wood wrote:
> > Oh. I think it'd be more readable to do "offset = start -
> > memstart_addr" and add offset instead of subtracting it.
>
> Yes, I agree. The reason that I use "offset = mem
On Wed, 2014-01-08 at 10:54 +0100, Andreas Schwab wrote:
> Michael Ellerman writes:
>
> > On Mon, 2013-12-30 at 15:31 +0100, Andreas Schwab wrote:
> >> GCC 4.8 now generates out-of-line vr save/restore functions when
> >> optimizing for size. They are needed for the raid6 altivec support.
> >
>
On Wed, Jan 08, 2014 at 03:58:08PM -0600, Scott Wood wrote:
> On Wed, 2014-01-08 at 13:01 +0800, Minghuan Lian wrote:
> > PowerPC uses structure pci_controller to describe PCI controller,
> > but ARM uses structure pci_sys_data. In order to support PowerPC
> > and ARM simultaneously, the patch adds
On Tue, Jan 07, 2014 at 05:52:31PM +0800, Wanpeng Li wrote:
> On Tue, Jan 07, 2014 at 04:41:36PM +0900, Joonsoo Kim wrote:
> >On Tue, Jan 07, 2014 at 01:21:00PM +1100, Anton Blanchard wrote:
> >> Index: b/mm/slub.c
> >> ===
> >> --- a
There is no barrier between something like ioremap() writing to
a PTE, and returning the value to a caller that may then store the
pointer in a place that is visible to other CPUs. Such callers
generally don't perform barriers of their own.
Even if callers of ioremap() and similar things did use
There are a few things that make the existing hw tablewalk handlers
unsuitable for e6500:
- Indirect entries go in TLB1 (though the resulting direct entries go in
TLB0).
- It has threads, but no "tlbsrx." -- so we need a spinlock and
a normal "tlbsx". Because we need this lock, hardware
This keeps usage coordinated for hugetlb and indirect entries, which
should make entry selection more predictable and probably improve overall
performance when mixing the two.
Signed-off-by: Scott Wood
---
v4: no change
arch/powerpc/mm/hugetlbpage-book3e.c | 51 +
On Wed, 2014-01-08 at 09:48 -0800, Olof Johansson wrote:
> > /* If it's a display, note it */
> > - memset(type, 0, sizeof(type));
> > - prom_getprop(stdout_node, "device_type", type, sizeof(type));
> > - if (strcmp(type, "display") == 0)
> > - prom_setprop(
On Wed, Jan 08, 2014 at 06:02:19PM -0600, Scott Wood wrote:
> On Wed, Jan 08, 2014 at 10:42:35AM +0800, Kevin Hao wrote:
> > On Tue, Jan 07, 2014 at 05:46:04PM -0600, Scott Wood wrote:
> > > Oh. I think it'd be more readable to do "offset = start -
> > > memstart_addr" and add offset instead of su
Hi Scott,
please see my comments inline.
On 01/09/2014 05:58 AM, Scott Wood wrote:
On Wed, 2014-01-08 at 13:01 +0800, Minghuan Lian wrote:
PowerPC uses structure pci_controller to describe PCI controller,
but ARM uses structure pci_sys_data. In order to support PowerPC
and ARM simultaneously,
Thanks for you review.
See my response inline.
Thanks,
Yuantian
> -Original Message-
> From: Wood Scott-B07421
> Sent: 2014年1月9日 星期四 2:44
> To: Mark Rutland
> Cc: Tang Yuantian-B29983; ga...@kernel.crashing.org;
> devicet...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org
> Subject: Re: 答复
Commit fbd7740fdfdf9475f switched pseries cpu idle handling from complete idle
loops to ppc_md.powersave functions. Earlier to this switch,
ppc64_runlatch_off() had to be called in each of the idle routines. But after
the switch this call is handled in arch_cpu_idle(),just before the call
to ppc_md
Hi Bjorn,
I am very sorry, The mail was filtered to another directory, I did not
notice update. The next versions will include these updates.
Thanks,
Minghuan
On 01/09/2014 08:12 AM, Bjorn Helgaas wrote:
On Wed, Jan 08, 2014 at 03:58:08PM -0600, Scott Wood wrote:
On Wed, 2014-01-08 at 13:0
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