Re: [PATCH] cpuidle: add freescale e500 family porcessors idle support

On Tue, 2014-04-01 at 16:33 +0800, Dongsheng Wang wrote: > From: Wang Dongsheng > > Add cpuidle support for e500 family, using cpuidle framework to > manage various low power modes. The new implementation will remain > compatible with original idle method. > > I have done test about power consum

Re: [PATCH V2 1/2] mm: move FAULT_AROUND_ORDER to arch/

From: Dave Hansen Date: Fri, 04 Apr 2014 09:18:43 -0700 > On 04/03/2014 11:27 PM, Madhavan Srinivasan wrote: >> This patch creates infrastructure to move the FAULT_AROUND_ORDER >> to arch/ using Kconfig. This will enable architecture maintainers >> to decide on suitable FAULT_AROUND_ORDER value b

Re: [PATCH V2 1/2] mm: move FAULT_AROUND_ORDER to arch/

On 04/03/2014 11:27 PM, Madhavan Srinivasan wrote: > This patch creates infrastructure to move the FAULT_AROUND_ORDER > to arch/ using Kconfig. This will enable architecture maintainers > to decide on suitable FAULT_AROUND_ORDER value based on > performance data for that architecture. Patch also ad

Re: [PATCH 09/20] of/fdt: create common debugfs

On 04/04/2014 03:32 PM, Rob Herring wrote: > On Fri, Apr 4, 2014 at 8:22 AM, Michal Simek wrote: >> On 04/04/2014 03:00 PM, Rob Herring wrote: >>> On Fri, Apr 4, 2014 at 7:16 AM, Michal Simek wrote: On 04/04/2014 12:16 AM, Rob Herring wrote: > From: Rob Herring > > Both powerpc

Re: [PATCH 09/20] of/fdt: create common debugfs

On Fri, Apr 4, 2014 at 8:22 AM, Michal Simek wrote: > On 04/04/2014 03:00 PM, Rob Herring wrote: >> On Fri, Apr 4, 2014 at 7:16 AM, Michal Simek wrote: >>> On 04/04/2014 12:16 AM, Rob Herring wrote: From: Rob Herring Both powerpc and microblaze have the same FDT blob in debugfs fe

Re: [PATCH 09/20] of/fdt: create common debugfs

On 04/04/2014 03:00 PM, Rob Herring wrote: > On Fri, Apr 4, 2014 at 7:16 AM, Michal Simek wrote: >> On 04/04/2014 12:16 AM, Rob Herring wrote: >>> From: Rob Herring >>> >>> Both powerpc and microblaze have the same FDT blob in debugfs feature. >>> Move this to common location and remove the power

Re: [PATCH V2 1/2] mm: move FAULT_AROUND_ORDER to arch/

On Fri, Apr 04, 2014 at 11:57:14AM +0530, Madhavan Srinivasan wrote: > Kirill A. Shutemov with faultaround patchset introduced > vm_ops->map_pages() for mapping easy accessible pages around > fault address in hope to reduce number of minor page faults. > > This patch creates infrastructure to move

Re: [PATCH 09/20] of/fdt: create common debugfs

On Fri, Apr 4, 2014 at 7:16 AM, Michal Simek wrote: > On 04/04/2014 12:16 AM, Rob Herring wrote: >> From: Rob Herring >> >> Both powerpc and microblaze have the same FDT blob in debugfs feature. >> Move this to common location and remove the powerpc and microblaze >> implementations. This feature

Re: [PATCH 09/20] of/fdt: create common debugfs

>> diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c >> index fa16a91..2085d47 100644 >> --- a/drivers/of/fdt.c >> +++ b/drivers/of/fdt.c >> @@ -20,6 +20,7 @@ >> #include >> #include >> #include >> +#include >> >> #include /* for COMMAND_LINE_SIZE */ >> #ifdef CONFIG_PPC >> @@ -1084,4 +

Re: [PATCH 09/20] of/fdt: create common debugfs

On 04/04/2014 12:16 AM, Rob Herring wrote: > From: Rob Herring > > Both powerpc and microblaze have the same FDT blob in debugfs feature. > Move this to common location and remove the powerpc and microblaze > implementations. This feature could become more useful when FDT > overlay support is add

[PATCH v3 2/2] ARM: dts: Append clock bindings for sai2 on VF610 platform

Since we added fours clock to the DT binding, we should update the current SAI dts/dtsi so as not to break their functions. Signed-off-by: Nicolin Chen Tested-by: Xiubo Li --- arch/arm/boot/dts/vf610.dtsi | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dt

[PATCH v3 1/2] ASoC: fsl_sai: Add clock controls for SAI

The SAI mainly has the following clocks: bus clock control and configuration registers and to generate synchronous interrupts and DMA requests. mclk1, mclk2, mclk3 to generate the bit clock when the receiver or transmitter is configured for an internally generated bit clock. S

[PATCH v3 0/2] ASoC: fsl_sai: Add bus clock and mclks with clock controls

This series of patches add clock controls to fsl_sai driver and updates the vf610.dtsi accordingly. Changelog v3: * Use int type for ret instead of u32. * Added Acked-by and Tested-by from Xiubo Li. v2: * Appended two extra mclks to the driver since SAI actually has three. * Renamed clock name

Re: [PATCH] ASoC: fsl_sai: Fix Bit Clock Polarity configurations

On Fri, Apr 04, 2014 at 03:09:47PM +0800, Nicolin Chen wrote: > The BCP bit in TCR4/RCR4 register rules as followings: > 0 Bit clock is active high with drive outputs on rising edge > and sample inputs on falling edge. > 1 Bit clock is active low with drive outputs on falling edge > and

RE: [PATCH v2 2/2] ARM: dts: Append clock bindings for sai2 on VF610 platform

> Subject: Re: [PATCH v2 2/2] ARM: dts: Append clock bindings for sai2 on VF610 > platform > > Hi Shawn, > >Thanks for the comments, but... > > On Wed, Apr 02, 2014 at 09:03:04PM +0800, Shawn Guo wrote: > > On Wed, Apr 02, 2014 at 06:10:20PM +0800, Nicolin Chen wrote: > > > Since we added f

Re: [PATCH 1/2] ASoC: fsl_sai: Add clock control for SAI

On Fri, Apr 04, 2014 at 05:43:12PM +0800, Xiubo Li-B47053 wrote: > > Subject: Re: [PATCH 1/2] ASoC: fsl_sai: Add clock control for SAI > > > > Hi Xiubo, > > > > On Fri, Apr 04, 2014 at 05:24:39PM +0800, Xiubo Li-B47053 wrote: > > > Hi, > > > > > > I have test this series on my Vybrid-TWR board an

RE: [PATCH 1/2] ASoC: fsl_sai: Add clock control for SAI

> Subject: Re: [PATCH 1/2] ASoC: fsl_sai: Add clock control for SAI > > Hi Xiubo, > > On Fri, Apr 04, 2014 at 05:24:39PM +0800, Xiubo Li-B47053 wrote: > > Hi, > > > > I have test this series on my Vybrid-TWR board and it works happily. > > You just checked the wrong version. I've sent a mail to

Re: [PATCH 1/2] ASoC: fsl_sai: Add clock control for SAI

Hi Xiubo, On Fri, Apr 04, 2014 at 05:24:39PM +0800, Xiubo Li-B47053 wrote: > Hi, > > I have test this series on my Vybrid-TWR board and it works happily. You just checked the wrong version. I've sent a mail to let people disregard this version and a newer v2. > > [...] > > diff --git a/sound/s

RE: [PATCH 1/2] ASoC: fsl_sai: Add clock control for SAI

Hi, I have test this series on my Vybrid-TWR board and it works happily. [...] > diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c > index 3847d2a..2d749df 100644 > --- a/sound/soc/fsl/fsl_sai.c > +++ b/sound/soc/fsl/fsl_sai.c > @@ -428,5 +428,18 @@ static int fsl_sai_startup(struct

[PATCH v2] powerpc/tm: Disable IRQ in tm_recheckpoint

We can't take an IRQ when we're about to do a trechkpt as our GPR state is set to user GPR values. We've hit this when running some IBM Java stress tests in the lab resulting in the following dump: cpu 0x3f: Vector: 700 (Program Check) at [c7eb3d40] pc: c0050074: restore_g

RE: [PATCH] ASoC: fsl_sai: Fix Bit Clock Polarity configurations

> > Is that possible for you to test those two clock patches for fsl_sai? > > I think most of us are waiting for your reply to it. And I'd really > like to move on to append clock dividing code into the driver so both > of vybrid and imx can easily enable the DAI master mode. > Certainly, I wi

Re: MPC8641 based custom board Kernel stuck at 1000Mhz core clock

On Thursday 03 April 2014 08:55 AM, sanjeev sharma wrote: Are you able to capture kernel logs ? Regards Sanjeev Sharma On Thu, Mar 27, 2014 at 10:01 PM, > wrote: On Thu, 27 Mar 2014 16:04:37 +0530, Ashish said: > Hi, > > I am using MPC8641-HP

Re: [PATCH] ASoC: fsl_sai: Fix Bit Clock Polarity configurations

Hi Xiubo, On Fri, Apr 04, 2014 at 03:37:00PM +0800, Xiubo Li-B47053 wrote: > > > Subject: [PATCH] ASoC: fsl_sai: Fix Bit Clock Polarity configurations > > > > The BCP bit in TCR4/RCR4 register rules as followings: > > 0 Bit clock is active high with drive outputs on rising edge > > and sam

RE: [PATCH] ASoC: fsl_sai: Fix Bit Clock Polarity configurations

> Subject: [PATCH] ASoC: fsl_sai: Fix Bit Clock Polarity configurations > > The BCP bit in TCR4/RCR4 register rules as followings: > 0 Bit clock is active high with drive outputs on rising edge > and sample inputs on falling edge. > 1 Bit clock is active low with drive outputs on falling

[PATCH v2] powerpc/le: enable RTAS events support

The current kernel code assumes big endian and parses RTAS events all wrong. The most visible effect is that we cannot honor EPOW events, meaning, for example, we cannot shut down a guest properly from the hypervisor. This new patch is largely inspired by Nathan's work: we get rid of all the bit f

Re: [PATCH V2 2/2] mm: add FAULT_AROUND_ORDER Kconfig paramater for powerpc

* Ingo Molnar wrote: > * Madhavan Srinivasan wrote: > > > Performance data for different FAULT_AROUND_ORDER values from 4 > > socket Power7 system (128 Threads and 128GB memory) is below. perf > > stat with repeat of 5 is used to get the stddev values. This patch > > create FAULT_AROUND_ORD

[PATCH] ASoC: fsl_sai: Fix Bit Clock Polarity configurations

The BCP bit in TCR4/RCR4 register rules as followings: 0 Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. 1 Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge. For all formats currently supported in t

Re: [PATCH V2 2/2] mm: add FAULT_AROUND_ORDER Kconfig paramater for powerpc

* Madhavan Srinivasan wrote: > Performance data for different FAULT_AROUND_ORDER values from 4 socket > Power7 system (128 Threads and 128GB memory) is below. perf stat with > repeat of 5 is used to get the stddev values. This patch create > FAULT_AROUND_ORDER Kconfig parameter and defaults it t