I spent ten minutes scratching my head, trying to work out where we
enabled relocation on interrupts for guest kernels. Expand the doco to
make it clear.
Signed-off-by: Michael Ellerman
---
arch/powerpc/kernel/setup_64.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/ar
pr_warn() is equal to pr_warning(), but the former is a bit more
formal according to commit fc62f2f ("kernel.h: add pr_warn for
symmetry to dev_warn, netdev_warn").
The patch replaces pr_warning() with pr_warn().
Signed-off-by: Gavin Shan
---
arch/powerpc/kernel/eeh.c| 16 ++
The patch allows PE (struct eeh_pe) instance to have auxillary data,
whose size is configurable on basis of platform. For PowerNV, the
auxillary data will be used to cache PHB diag-data for that PE
(frozen PE or fenced PHB). In turn, we can retrieve the diag-data
at any later points.
It's useful f
There are multiple global EEH flags. Almost each flag has its own
accessor, which doesn't make sense. The patch refactors EEH flag
accessors so that they look unified:
eeh_add_flag(): Add EEH flag
eeh_clear_flag(): Clear EEH flag
eeh_has_flag(): Check if one specific flag has been set
It's followup of commit ddf0322a ("powerpc/powernv: Fix endianness
problems in EEH"). The patch helps to get non-endian-dependent
diag-data.
Cc: Guo Chao
Signed-off-by: Gavin Shan
---
arch/powerpc/include/asm/opal.h | 128 +++---
arch/powerpc/platforms/powernv/
The patch prints 4 PCIE or AER config registers each line, which
is part of the EEH log so that it looks a bit more compact.
Suggested-by: Benjamin Herrenschmidt
Signed-off-by: Gavin Shan
---
v2: Siplified condition to output buffer and renamed "i" to "l".
---
arch/powerpc/kernel/eeh.c | 38 +++
The patchset is EEH cleanup and expected to be merged during 3.17
window. The the patchset is expected to be applied after:
| EEH support for guest
| 2 more bug fixes for EEH support for guest
| M64 related EEH changes
| 2 bug fixes from Mike Qiu
|
+-> The current patchset
Excep
According to the experiment I did, PCI config access is blocked
on P7IOC frozen PE by hardware, but PHB3 doesn't do that. That
means we always get 0xFF's while dumping PCI config space of the
frozen PE on P7IOC. We don't have the problem on PHB3. So we have
to enable I/O prioir to collecting error
On Wed, Jul 16, 2014 at 08:24:30PM +0800, Guo Chao wrote:
>This patch enables M64 aperatus for PHB3.
>
>We already had platform hook (ppc_md.pcibios_window_alignment) to affect
>the PCI resource assignment done in PCI core so that each PE's M32 resource
>was built on basis of M32 segment size. Simi
The POWER8 processor has a Micro Partition Prefetch Engine, which is
a fancy way of saying "has way to store and load contents of L2 or
L2+MRU way of L3 cache". We initiate the storing of the log (list of
addresses) using the logmpp instruction and start restore by writing
to a SPR.
The logmpp ins
On 07/15/2014 07:24 PM, Alexey Kardashevskiy wrote:
> Guests might put new TCEs without clearing them first and the PAPR spec
> allows that.
>
> This adds put_page() for TCEs which we just replaced.
>
> Signed-off-by: Alexey Kardashevskiy
> ---
> arch/powerpc/kernel/iommu.c | 10 +-
> 1
On Wed, Jul 16, 2014 at 5:12 PM, Nathan Fontenot wrote:
> On 07/16/2014 05:26 PM, Grant Likely wrote:
>> On Wed, Jul 16, 2014 at 2:57 PM, Grant Likely
>> wrote:
>>> On Wed, Jul 16, 2014 at 12:30 PM, Tyrel Datwyler
>>> wrote:
On 07/15/2014 10:33 PM, Grant Likely wrote:
> I've got anothe
On 07/16/2014 05:26 PM, Grant Likely wrote:
> On Wed, Jul 16, 2014 at 2:57 PM, Grant Likely wrote:
>> On Wed, Jul 16, 2014 at 12:30 PM, Tyrel Datwyler
>> wrote:
>>> On 07/15/2014 10:33 PM, Grant Likely wrote:
I've got another question about powerpc reconfiguration. I was looking
at the
On Wed, Jul 16, 2014 at 2:57 PM, Grant Likely wrote:
> On Wed, Jul 16, 2014 at 12:30 PM, Tyrel Datwyler
> wrote:
>> On 07/15/2014 10:33 PM, Grant Likely wrote:
>>> I've got another question about powerpc reconfiguration. I was looking
>>> at the dlpar_configure_connector() function in dlpar.c. I
On Sat, Jul 12, 2014 at 01:21:08PM +0200, Alexander Gordeev wrote:
> There are no archs that override arch_msi_check_device()
> hook. Remove it as it is completely redundant.
>
> If an arch would need to check MSI/MSI-X possibility for a
> device it should make it within arch_setup_msi_irqs() hook
On Wed, Jul 16, 2014 at 12:30 PM, Tyrel Datwyler
wrote:
> On 07/15/2014 10:33 PM, Grant Likely wrote:
>> I've got another question about powerpc reconfiguration. I was looking
>> at the dlpar_configure_connector() function in dlpar.c. I see that the
>> function has the ability to process multiple
Signed-off-by: Andy Fleming
Signed-off-by: Shaohui Xie
Signed-off-by: Shruti Kanetkar
---
arch/powerpc/configs/corenet32_smp_defconfig | 1 +
arch/powerpc/configs/corenet64_smp_defconfig | 1 +
arch/powerpc/platforms/85xx/corenet_generic.c | 3 +++
3 files changed, 5 insertions(+)
diff --git
From: Andy Fleming
Signed-off-by: Andy Fleming
Signed-off-by: Shaohui Xie
Signed-off-by: Shruti Kanetkar
---
arch/powerpc/configs/corenet32_smp_defconfig | 2 ++
arch/powerpc/configs/corenet64_smp_defconfig | 2 ++
arch/powerpc/platforms/85xx/corenet_generic.c | 3 +++
3 files changed, 7 in
The device tree binding(s) document has fallen out of sync with the
driver code. Update the list of supported devices to reflect current
driver capabilities
Signed-off-by: Shruti Kanetkar
---
Documentation/devicetree/bindings/net/fsl-tsec-phy.txt | 11 ++-
1 file changed, 10 insertions(+
FMan 1 Gb/s MACs (dTSEC and mEMAC) have support for SGMII PHYs.
Add support for the internal SerDes TBI PHYs
Based on prior work by Andy Fleming
Signed-off-by: Shruti Kanetkar
---
arch/powerpc/boot/dts/fsl/b4860si-post.dtsi | 28 +
arch/powerpc/boot/dts/fsl/b4si-post.dtsi| 51 +++
Based on prior work by Andy Fleming
Signed-off-by: Shruti Kanetkar
---
arch/powerpc/boot/dts/b4860qds.dts | 56 +++
arch/powerpc/boot/dts/b4qds.dtsi | 45 ++
arch/powerpc/boot/dts/p1023rdb.dts | 19 +++
arch/powerpc/boot/dts/p2041rdb.dts | 87 +++
arch/powerpc/boot/dts/p30
This document covers FManv2 and FManv3 mEMAC MDIO
Signed-off-by: Shruti Kanetkar
---
.../devicetree/bindings/net/fsl-xgmac-phy.txt | 29 ++
1 file changed, 29 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/fsl-xgmac-phy.txt
diff --git a/Document
On 07/15/2014 10:33 PM, Grant Likely wrote:
> I've got another question about powerpc reconfiguration. I was looking
> at the dlpar_configure_connector() function in dlpar.c. I see that the
> function has the ability to process multiple nodes with additional
> sibling and child nodes. It appears to
* Masami Hiramatsu wrote:
> (2014/07/15 16:16), Benjamin Herrenschmidt wrote:
> > On Tue, 2014-07-15 at 13:19 +1000, Michael Ellerman wrote:
> >
> >>> Signed-off-by: Masami Hiramatsu
> >>> Reported-by: Tony Luck
> >>> Tested-by: Tony Luck
> >>> Cc: Michael Ellerman
> >>
> >> Tested-by: Mich
On Wed, Jul 16, 2014 at 08:30:55AM +, David Laight wrote:
>From: Gavin Shan
>> The patch prints 4 PCIE or AER config registers each line, which
>> is part of the EEH log so that it looks a bit more compact.
>...
>> -for (i=0; i<=8; i++) {
>> +for (i=0, j=0; i<=8; i++) {
From: Gavin Shan
The patch handles compound PE for EEH backend. If one specific
PE in compound group has been frozen, we enforces to freeze
all PEs in the group. If we're enable DMA or MMIO for one PE
in compound group, DMA or MMIO of all PEs in the group will be
enabled.
Signed-off-by: Gavin Sh
From: Gavin Shan
The PCI config accessors check for PE frozen state and clear it if
EEH isn't functional. The patch handles compound PE in config accessors
if PHB supports it. For consistency, all PEs will be put into frozen
state if any one in compound group gets frozen by hardware.
Signed-off-
From: Gavin Shan
The patch introduces 3 PHB callbacks: compound PE state retrieval,
force freezing and unfreezing compound PE. The PCI config accessors
and PowerNV EEH backend can use them in subsequent patches.
We don't export the capability of compound PE to EEH core, which
helps avoiding more
From: Gavin Shan
Function ioda_eeh_get_state() is used to fetch EEH state for PHB
or PE. We're going to support compound PE and the function becomes
more complicated with that. The patch splits the function into two
functions for PHB and PE cases separately to improve readability.
Signed-off-by:
From: Gavin Shan
For compound PE, all PEs should be frozen if any one in the group
becomes frozen. Unfortunately, hardware doesn't always do that
automatically with help of PELTV. So we have to flirt with
PESTA/B a bit to freeze all PEs for the case.
The patch sychronizes with firmware hearder a
This patch enables M64 aperatus for PHB3.
We already had platform hook (ppc_md.pcibios_window_alignment) to affect
the PCI resource assignment done in PCI core so that each PE's M32 resource
was built on basis of M32 segment size. Similarly, we're using that for
M64 assignment on basis of M64 segm
This version is rebased on top of Gavin's patches of EEH support for guest and
related fixes which are supposed to be merged in 3.17.
Changed from v1:
* Don't overwrite PE flags
* Don't return segment alignment if M64 is not supported
* Output M64 total size and segment siz
On Wed, Jul 16, 2014 at 08:24:49AM +, David Laight wrote:
>From: Gavin Shan
>> There are multiple global EEH flags. Almost each flag has its own
>> accessor, which doesn't make sense. The patch refactors EEH flag
>> accessors so that they look unified:
>>
>> eeh_add_flag(): Add EEH flag
>
From: Gavin Shan
> The patch prints 4 PCIE or AER config registers each line, which
> is part of the EEH log so that it looks a bit more compact.
...
> - for (i=0; i<=8; i++) {
> + for (i=0, j=0; i<=8; i++) {
> eeh_ops->read_config(dn, cap+4*i, 4, &cfg)
From: Gavin Shan
> There are multiple global EEH flags. Almost each flag has its own
> accessor, which doesn't make sense. The patch refactors EEH flag
> accessors so that they look unified:
>
> eeh_add_flag(): Add EEH flag
eeh_set_flag() ??
> eeh_clear_flag(): Clear EEH flag
> eeh_has_f
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