Le 05/01/2015 19:30, Joakim Tjernlund a écrit :
On Tue, 2014-12-16 at 16:03 +0100, Christophe Leroy wrote:
CR only needs to be preserved when checking if we are handling a kernel address.
So we can preserve CR in a register:
- In ITLBMiss, check is done only when CONFIG_MODULES is defined. Othe
Le 05/01/2015 19:12, Joakim Tjernlund a écrit :
On Mon, 2014-12-22 at 11:14 +0100, Christophe Leroy wrote:
On powerpc 8xx, in TLB entries, 0x400 bit is set to 1 for read-only pages
and is set to 0 for RW pages. So we should use _PAGE_RO instead of _PAGE_RW
Signed-off-by: Christophe Leroy
Hi
Hello,
While doing some performance testing of a KVM guest on a PPC platform, I
noticed that there's a read of the CPU_WHOAMI register after each MPIC
EOI [1]. This has been present since the initial implementation of the
MPIC driver [2]. In a KVM virtualized environment, this results in an
a
[CC related ppl]
On Mon, Jan 05, 2015 at 12:10:54PM -0600, Scott Wood wrote:
> On Mon, 2015-01-05 at 18:46 +0100, Andreas Mohr wrote:
> > Hi,
> >
> > > I was curious why the mpic_cpu_read(MPIC_INFO(CPU_WHOAMI)) was there in
> > > the first place and if it's still needed. If it's still required, I
On Tue, 2014-12-16 at 16:03 +0100, Christophe Leroy wrote:
> All accessed to PGD entries are done via 0(r11).
> By using lower part of swapper_pg_dir as load index to r11, we can remove the
> ori instruction.
>
> Signed-off-by: Christophe Leroy
Nice :)
Acked-by: Joakim Tjernlund
>
> ---
> a
On Tue, 2014-12-16 at 16:03 +0100, Christophe Leroy wrote:
> CR only needs to be preserved when checking if we are handling a kernel
> address.
> So we can preserve CR in a register:
> - In ITLBMiss, check is done only when CONFIG_MODULES is defined. Otherwise we
> don't need to do anything at al
On Tue, 2014-12-16 at 16:03 +0100, Christophe Leroy wrote:
> By default, TASK_SIZE is set to 0x8000 for PPC_8xx, which is most likely
> sufficient for most cases. However, kernel configuration allows to set
> TASK_SIZE
> to another value, so the 8xx shall handle it.
On 8xx I would be just as
On Tue, 2014-12-16 at 16:03 +0100, Christophe Leroy wrote:
> Kernel MMU handling code handles validity of entries via _PMD_PRESENT which
> corresponds to V bit in MD_TWC and MI_TWC. When the V bit is not set, MPC8xx
> triggers TLBError exception. So we don't have to check that and branch ourself
>
On Mon, 2014-12-22 at 11:14 +0100, Christophe Leroy wrote:
> On powerpc 8xx, in TLB entries, 0x400 bit is set to 1 for read-only pages
> and is set to 0 for RW pages. So we should use _PAGE_RO instead of _PAGE_RW
>
> Signed-off-by: Christophe Leroy
Hi Christophe, been meaning to look over all y
On Tue, 2014-12-16 at 16:03 +0100, Christophe Leroy wrote:
> L1 base address is now aligned so we can insert L1 index into r11 directly and
> then preserve r10
>
> Signed-off-by: Christophe Leroy
Acked-by: Joakim Tjernlund
>
> ---
> arch/powerpc/kernel/head_8xx.S | 34 +++---
On Mon, 2015-01-05 at 18:46 +0100, Andreas Mohr wrote:
> Hi,
>
> > I was curious why the mpic_cpu_read(MPIC_INFO(CPU_WHOAMI)) was there in
> > the first place and if it's still needed. If it's still required, I
> > guess a better approach is to eliminate the call only if the kernel is
> > running
Hi,
> I was curious why the mpic_cpu_read(MPIC_INFO(CPU_WHOAMI)) was there in
> the first place and if it's still needed. If it's still required, I
> guess a better approach is to eliminate the call only if the kernel is
> running on the KVM guest side, where the MPIC is emulated and no longer
> r
On Mon, Jan 5, 2015 at 1:12 PM, Michael Tessier
wrote:
> If sound is ok when using only 1 codec and becomes choppy when adding a
> second codec, then it means that this issue is still in the 3.x kernel. This
> answer will tell me if it is worth working on using a newer kernel or not.
> I have to
On Mon, 5 Jan 2015, Michael Tessier wrote:
> > > Hi,
> > >
> > > I am dealing with a USB EHCI driver bug. Here is the info:
> > >
> > > My configuration:
> > > -
> > >
> > > Host: Freescale i.MX512 with ARM Cortex A8 (USB 2.0 host controller)
> > > Linux kernel: 2.6.31, using E
For nohash powerpc, when we run out of contexts, contexts are freed by stealing
used contexts in-turn. When a victim has been selected, the associated TLB
entries are freed using _tlbil_pid(). Unfortunatly, on the PPC 8xx, _tlbil_pid()
does a tlbia, hence flushes ALL TLB entries and not only the on
>
> On Mon, 15 Dec 2014, Michael Tessier wrote:
>
> > Hi,
> >
> > I am dealing with a USB EHCI driver bug. Here is the info:
> >
> > My configuration:
> > -
> >
> > Host: Freescale i.MX512 with ARM Cortex A8 (USB 2.0 host controller)
> > Linux kernel: 2.6.31, using EHCI USB driv
For nohash powerpc, when we run out of contexts, contexts are freed by stealing
used contexts in-turn. When a victim has been selected, the associated TLB
entries are freed using _tlbil_pid(). Unfortunatly, on the PPC 8xx, _tlbil_pid()
does a tlbia, hence flushes ALL TLB entries and not only the on
On Sun, Jan 04, 2015 at 02:36:01PM +0100, SF Markus Elfring wrote:
> /* unmap PCI memory space, mapped during device init. */
> - for (idx = 0; idx < HPI_MAX_ADAPTER_MEM_SPACES; idx++) {
> - if (pci.ap_mem_base[idx])
> - iounmap(pci.ap_mem_base[idx]);
> -
Some of FSL SoCs like T1040 has new version of UART controller which
can support 64byte FiFo.
To enable 64 byte support, following needs to be done:
-FCR[EN64] needs to be programmed to 1 to enable it.
-Also, when FCR[EN64]==1, RTL bits to be used as below
to define various Receive Trigger Levels:
Hello Scott,
Is this v3 OK?
Best Regards,
Shaohui Xie
> -Original Message-
> From: shh@gmail.com [mailto:shh@gmail.com]
> Sent: Tuesday, December 23, 2014 3:58 PM
> To: linuxppc-dev@lists.ozlabs.org; devicet...@vger.kernel.org; Wood
> Scott-B07421
> Cc: Medve Emilian-EMMEDVE1; X
> -Original Message-
> From: Emil Medve [mailto:emilian.me...@freescale.com]
> Sent: Monday, January 05, 2015 5:29 PM
> To: Xie Shaohui-B21989; linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421
> Cc: Andy Fleming; Kanetkar Shruti-B44454
> Subject: Re: [PATCH 2/2] powerpc/config: enable mdio
pte_protnone_numa is only safe to use after VMA checks for PROT_NONE are
complete. Treating a real PROT_NONE PTE as a NUMA hinting fault is going
to result in strangeness so add a check for it. BUG_ON looks like overkill
but if this is hit then it's a serious bug that could result in corruption
so
If a PTE or PMD is already marked NUMA when scanning to mark entries
for NUMA hinting then it is not necessary to update the entry and
incur a TLB flush penalty. Avoid the avoidhead where possible.
Signed-off-by: Mel Gorman
---
mm/huge_memory.c | 14 --
mm/mprotect.c| 4
2
Commit b38af4721f59 ("x86,mm: fix pte_special versus pte_numa") adjusted
the pte_special check to take into account that a special pte had SPECIAL
and neither PRESENT nor PROTNONE. Now that NUMA hinting PTEs are no
longer modifying _PAGE_PRESENT it should be safe to restore the original
pte_special
Faults on the huge zero page are pointless and there is a BUG_ON
to catch them during fault time. This patch reintroduces a check
that avoids marking the zero page PAGE_NONE.
Signed-off-by: Mel Gorman
---
include/linux/huge_mm.h | 3 ++-
mm/huge_memory.c| 13 -
mm/memory.c
With PROT_NONE, the traditional page table manipulation functions are
sufficient.
Signed-off-by: Mel Gorman
Acked-by: Linus Torvalds
Acked-by: Aneesh Kumar
Tested-by: Sasha Levin
---
include/linux/huge_mm.h | 3 +--
mm/huge_memory.c| 33 +++--
mm/memory.c
This patch removes the NUMA PTE bits and associated helpers. As a side-effect
it increases the maximum possible swap space on x86-64.
One potential source of problems is races between the marking of PTEs
PROT_NONE, NUMA hinting faults and migration. It must be guaranteed that
a PTE being protected
ppc64 should not be depending on DSISR_PROTFAULT and it's unexpected
if they are triggered. This patch adds warnings just in case they
are being accidentally depended upon.
Signed-off-by: Mel Gorman
Acked-by: Aneesh Kumar K.V
Tested-by: Sasha Levin
---
arch/powerpc/mm/copro_fault.c | 8 ++
Changelog since V4
o Rebase to 3.19-rc2(mel)
Changelog since V3
o Minor comment update (benh)
o Add ack'ed bys
Changelog since V2
o Rename *_protnone_numa to _protnone and extend docs (linus)
o Rebase t
This is a preparatory patch that introduces protnone helpers for automatic
NUMA balancing.
Signed-off-by: Mel Gorman
Acked-by: Linus Torvalds
Acked-by: Aneesh Kumar K.V
Tested-by: Sasha Levin
---
arch/powerpc/include/asm/pgtable.h | 16
arch/x86/include/asm/pgtable.h | 16
Convert existing users of pte_numa and friends to the new helper. Note
that the kernel is broken after this patch is applied until the other
page table modifiers are also altered. This patch layout is to make
review easier.
Signed-off-by: Mel Gorman
Acked-by: Linus Torvalds
Acked-by: Aneesh Kuma
A transhuge NUMA hinting fault may find the page is migrating and should
wait until migration completes. The check is race-prone because the pmd
is deferenced outside of the page lock and while the race is tiny, it'll
be larger if the PMD is cleared while marking PMDs for hinting fault.
This patch
Hello Shao-Hui,
On 01/03/2015 10:58 PM, Xie Shaohui-B21989 wrote:
> Hello Emil,
>
> The patches sent by Shruti were marked as "Changes Requested" over 5 months.
> to me if the patches do need changes, the possible changes seems not in
> 'config' but in corenet_generic.c.
It was part of a serie
33 matches
Mail list logo
