> On Fri, 2015-01-30 at 19:08 +0700, Arseny Solokha wrote:
>> MMU_NO_CONTEXT is conditionally defined as 0 or (unsigned int)-1.
>
> For nohash it is specifically -1.
>> However, in __flush_tlb_page() a corresponding variable is only tested
>> for open coded 0, which can cause NULL pointer derefer
These duties include do_timer to update jiffies and broadcast wakeups on those
platforms which do not have an external device to handle wakeup of cpus from
deep
idle states. The handover of these duties is not robust against a cpu offline
operation today.
The do_timer duty is handed over in the C
On Thu, Jan 15, 2015 at 10:28:04AM +0800, Wei Yang wrote:
> On PowrNV platform, resource position in M64 implies the PE# the resource
> belongs to. In some particular case, adjustment of a resource is necessary
> to locate it to a correct position in M64.
>
> This patch introduces a function to sh
On Fri, 2015-01-30 at 19:08 +0700, Arseny Solokha wrote:
> MMU_NO_CONTEXT is conditionally defined as 0 or (unsigned int)-1.
For nohash it is specifically -1.
> However, in __flush_tlb_page() a corresponding variable is only tested
> for open coded 0, which can cause NULL pointer dereference if
From: Cody P Schafer
This adds (in req-gen/) a framework for defining gpci counter requests.
It uses macro magic similar to ftrace.
Also convert the existing hv-gpci request structures and enum values to
use the new framework (and adjust old users of the structs and enum
values to cope with chan
From: Cody P Schafer
Add the remaining gpci requests that contain counters suitable for use
by perf. Omit those that don't contain any counters (but note their
ommision).
Signed-off-by: Cody P Schafer
Signed-off-by: Sukadev Bhattiprolu
---
Changelog[v6]
[Jiri Olsa, Sukadev Bhattiprolu
From: Cody P Schafer
Signed-off-by: Cody P Schafer
Signed-off-by: Sukadev Bhattiprolu
---
Changelog[v6]
Update Contact info to Linux on Power Developer list
.../testing/sysfs-bus-event_source-devices-hv_24x7 | 22 ++
1 file changed, 22 insertions(+)
diff --git a/D
Define a lite version of the EVENT_DEFINE_RANGE_FORMAT() that avoids
defining helper functions for the bit-field ranges.
Signed-off-by: Sukadev Bhattiprolu
---
arch/powerpc/perf/hv-common.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/powerpc/perf/hv-common.h b/arch/power
From: Cody P Schafer
Retrieves and parses the 24x7 catalog on POWER systems that supply it
(right now, only POWER 8). Events are exposed via sysfs in the standard
fashion, and are all parameterized.
$ cd /sys/bus/event_source/devices/hv_24x7/events
$ cat HPM_CS_FROM_L4_LDATA__PH
From: Cody P Schafer
(struct perf_pmu_events_attr) is defined in include/linux/perf_event.h,
but the only "show" for it is in x86 and contains x86 specific stuff.
Make a generic one for those of us who are just using the event_str.
Signed-off-by: Cody P Schafer
Signed-off-by: Sukadev Bhattipro
From: Cody P Schafer
Helper for constructing static struct perf_pmu_events_attr s.
Signed-off-by: Cody P Schafer
Signed-off-by: Sukadev Bhattiprolu
Acked-by: Jiri Olsa
---
Changelog[v7]:
[Jiri Olsa] Initialize 'id' field in perf_pmu_events_attr also.
include/linux/perf_event.h | 7 +
Description of "event parameters" from the documentation patch:
Event parameters are a basic way for partial events to be specified in
sysfs with per-event names given to the fields that need to be filled in
when using a particular event.
It is intended for supporting cases where
On Fri, 2015-01-30 at 11:41 +0100, Gabriel Paubert wrote:
> By the way, I wonder where the SAVE_EVR/REST_EVR macros are used. I only
> see the definitions, no use in a 3.18 source tree.
SAVE_EVR is used by SAVE_2EVRs, which is used by SAVE_4EVRS, etc.
The 32EVRS version is used in load_up_spe() a
On Friday 30 January 2015 20:44:00 Hari Bathini wrote:
> With minor checks, we can move most of the code for nvram
> under pseries to a common place to be re-used by other
> powerpc platforms like powernv. This patch moves such
> common code to arch/powerpc/kernel/nvram_64.c file.
>
> Signed-off-b
This patch extends pstore, a generic interface to platform dependent
persistent storage, support for powernv platform to capture certain
useful information, during dying moments. Such support is already in
place for pseries platform. This patch re-uses most of that code.
It is a common practice
This patch adds a new PPC64 partition type to be used for opal
specific nvram partition. A new partition type is needed as none
of the existing type matches this partition type.
Signed-off-by: Hari Bathini
Cc: Anton Vorontsov
Cc: Colin Cross
Cc: Kees Cook
Cc: Tony Luck
---
fs/pstore/inode.c
With minor checks, we can move most of the code for nvram
under pseries to a common place to be re-used by other
powerpc platforms like powernv. This patch moves such
common code to arch/powerpc/kernel/nvram_64.c file.
Signed-off-by: Hari Bathini
---
arch/powerpc/include/asm/nvram.h | 50
This patch series adds pstore support on powernv platform to
read different nvram partitions and write compressed data to
oops-log nvram partition. As pseries platform already has
pstore support, this series moves most of the common code
for pseries and powernv platforms to a common file. Tested
th
Em Thu, Jan 29, 2015 at 03:28:43PM +1100, Michael Ellerman escreveu:
> On Mon, 2015-01-26 at 17:43 -0800, Sukadev Bhattiprolu wrote:
> > Description of "event parameters" from the documentation patch:
> >
> > Cody P Schafer (6):
> > perf: provide sysfs_show for struct perf_pmu_events_attr
> >
[PATCH v2 3/3] SHA256 for PPC/SPE - kernel config
Integrate the module into the kernel config tree.
Signed-off-by: Markus Stockhausen
diff --git a/arch/powerpc/crypto/Makefile b/arch/powerpc/crypto/Makefile
index 2926fb9..a07e763 100644
--- a/arch/powerpc/crypto/Makefile
+++ b/arch/powerpc/cryp
[PATCH v2 2/3] SHA256 for PPC/SPE - glue
Glue code for crypto infrastructure. Call the assembler
code where required. Disable preemption during calculation
and enable SPE instructions in the kernel prior to the
call. Avoid to disable preemption for too long.
Take a little care about small input
[PATCH v2 1/3] SHA256 for PPC/SPE - assembler
This is the assembler code for SHA256 implementation with
the SIMD SPE instruction set. Although being only a 32 bit
architecture GPRs are extended to 64 bit presenting two
32 bit values. With the enhanced instruction set we can
operate on them in para
[PATCH v2 0/3] SHA256 for PPC/SPE
The following patches add support for SIMD accelerated SHA256
calculation on PPC processors with SPE instruction set. The
implementation takes care of the following constraints:
- independant of processor endianess
- save SPE registers for interrupt context com
Hello Scott,
On 01/29/2015 11:03 PM, Scott Wood wrote:
> On Mon, Dec 08, 2014 at 04:29:20AM -0600, Emil Medve wrote:
>> From: Kumar Gala
>>
>> Change-Id: If643fa5ba0a903aef8f5056a2c90ebecc995b760
>> Signed-off-by: Kumar Gala
>> Signed-off-by: Geoff Thorpe
>> Signed-off-by: Hai-Ying Wang
>> Si
MMU_NO_CONTEXT is conditionally defined as 0 or (unsigned int)-1. However,
in __flush_tlb_page() a corresponding variable is only tested for open
coded 0, which can cause NULL pointer dereference if `mm' argument was
legitimately passed as such.
Bail out early in case the first argument is NULL, t
I have been using the driver with this modification for the past 6 months
and it has been stable in an industrial environment.I had made a few other
changes that also improve reliability (using ppc in_8 and out_8 and eieio
barriers to ensure in-order execution. This lets you remove the unneeded
dou
> Von: Conor O'Gorman [i...@conorogorman.net]
> Gesendet: Freitag, 30. Januar 2015 13:02
> An: Markus Stockhausen; linux-cry...@vger.kernel.org
> Cc: linuxppc-dev@lists.ozlabs.org
> Betreff: Re: [PATCH v1 0/3] SHA256 for PPC/SPE
>
> On 24/01/15 21:10, Markus Stockhausen wrote:
> > [PATCH v1 0/3] S
On 24/01/15 21:10, Markus Stockhausen wrote:
[PATCH v1 0/3] SHA256 for PPC/SPE
The following patches add support for SIMD accelerated SHA256
calculation on PPC processors with SPE instruction set. The
Nice boost.
Many of the SoCs with e500 core have crypto hardware accelerators. How
does thi
On Fri, Jan 30, 2015 at 09:39:41AM +, Markus Stockhausen wrote:
> > Von: Gabriel Paubert [paub...@iram.es]
> > Gesendet: Freitag, 30. Januar 2015 09:49
> > An: Markus Stockhausen
> > Cc: Scott Wood; linuxppc-dev@lists.ozlabs.org; Herbert Xu
> > Betreff: Re: AW: SPE & Interrupt context (was how
ISR should not return IRQ_HANDLED for not handling anything.
This patch fixes the return value of ISR for the same case.
Signed-off-by: Amit Singh Tomar
---
drivers/i2c/busses/i2c-mpc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/i2c/busses/i2c-mpc.c b/driver
> Von: Gabriel Paubert [paub...@iram.es]
> Gesendet: Freitag, 30. Januar 2015 09:49
> An: Markus Stockhausen
> Cc: Scott Wood; linuxppc-dev@lists.ozlabs.org; Herbert Xu
> Betreff: Re: AW: SPE & Interrupt context (was how to make use of SPE
> instructions)
>
> > ...
> > - I must already save severa
On Fri, Jan 30, 2015 at 05:37:29AM +, Markus Stockhausen wrote:
> > Von: Scott Wood [scottw...@freescale.com]
> > Gesendet: Freitag, 30. Januar 2015 01:49
> > An: Markus Stockhausen
> > Cc: Michael Ellerman; linuxppc-dev@lists.ozlabs.org; Herbert Xu
> > Betreff: Re: AW: SPE & Interrupt context
Hi Michael,
On Fri, Jan 30, 2015 at 5:09 AM, Michael Ellerman wrote:
> On Wed, 2015-14-01 at 13:51:57 UTC, Geert Uytterhoeven wrote:
>> of_find_node_by_name() calls of_node_put() on its "from" parameter,
>> which must not be done on "master", as it's still in use, and will be
>> released manually
33 matches
Mail list logo
