Signed-off-by: Wei Yang
---
arch/powerpc/platforms/powernv/pci-ioda.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c
b/arch/powerpc/platforms/powernv/pci-ioda.c
index 1776b36..f1fc7cf 100644
--- a/arch/powerpc/platforms/powernv/pc
When IOV BAR is bigger than 64MB, we just reserve a power_2 value.
I guess this change is lost during the rebase.
Signed-off-by: Wei Yang
---
arch/powerpc/platforms/powernv/pci-ioda.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/platforms/powernv/pci-i
__pci_read_base() will return 1 when it is a 64-bit BAR, which makes the
resource index not correct. So i could not be the index in this case.
Signed-off-by: Wei Yang
---
drivers/pci/iov.c |6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/iov.c b/drivers/pc
Bjorn,
I had a try on your pci/virtualization branch, it works fine after applying
following three patches. The reason is written in the change log. And I have
tried, they could apply cleanly with the original one.
For the pnv_pci_ioda_fixup_sriov(), which you suggest to merge in sriov_init()
I f
On 02/05/2015 12:32 AM, Alexander Graf wrote:
>
>
> On 03.02.15 01:12, Alex Williamson wrote:
>> On Thu, 2015-01-29 at 20:21 +1100, Alexey Kardashevskiy wrote:
>>> Modern IBM POWERPC systems support multiple (currently two) TCE tables
>>> per IOMMU group (a.k.a. PE). This adds a powerpc_iommu con
On 02/04/2015 05:08 PM, Paul Mackerras wrote:
> On Thu, Jan 29, 2015 at 08:21:53PM +1100, Alexey Kardashevskiy wrote:
>> At the moment writing new TCE value to the IOMMU table fails with EBUSY
>> if there is a valid entry already. However PAPR specification allows
>> the guest to write new TCE valu
Greetings Benjamin and others,
I am wondering why this code has not been removed:
for (; ch; temp++) { /* FIXME: This is ugly, but should work, as a \0 byte is
not a valid command code */
anslcd_write_byte_ctrl ( ch );
__get_user(ch, temp);
On Wed, Feb 04, 2015 at 02:53:13PM -0600, Bjorn Helgaas wrote:
>On Wed, Feb 04, 2015 at 11:34:09AM +0800, Wei Yang wrote:
>> On Tue, Feb 03, 2015 at 06:19:26PM -0600, Bjorn Helgaas wrote:
>> >On Tue, Feb 03, 2015 at 03:01:43PM +0800, Wei Yang wrote:
>> >> The actual IOV BAR range is determined by t
On Wed, Feb 04, 2015 at 04:16:30PM -0600, Emil Medve wrote:
> Hello Greg,
>
>
> Thanks for looking at this
>
> On 02/04/2015 12:40 PM, Greg KH wrote:
> > On Wed, Feb 04, 2015 at 08:48:32AM -0600, Emil Medve wrote:
> >>
> >> Hello,
> >>
> >>
> >> This is the first attempt to publish the Freescale
On Wed, Feb 04, 2015 at 05:44:42PM -0600, Bjorn Helgaas wrote:
>On Thu, Jan 15, 2015 at 10:27:50AM +0800, Wei Yang wrote:
>> This patchset enables the SRIOV on POWER8.
>>
>> The gerneral idea is put each VF into one individual PE and allocate required
>> resources like MMIO/DMA/MSI. The major diff
On Wed, Feb 04, 2015 at 04:05:18PM -0600, Bjorn Helgaas wrote:
>On Thu, Jan 15, 2015 at 10:28:06AM +0800, Wei Yang wrote:
>> M64 aperture size is limited on PHB3. When the IOV BAR is too big, this
>> will exceed the limitation and failed to be assigned.
>>
>> This patch introduce a different mecha
On Thu, Jan 15, 2015 at 10:27:50AM +0800, Wei Yang wrote:
> This patchset enables the SRIOV on POWER8.
>
> The gerneral idea is put each VF into one individual PE and allocate required
> resources like MMIO/DMA/MSI. The major difficulty comes from the MMIO
> allocation and adjustment for PF's IOV
On Thu, Jan 15, 2015 at 10:27:56AM +0800, Wei Yang wrote:
> In order to enable SRIOV on PowerNV platform, the PF's IOV BAR needs to be
> adjusted:
> 1. size expaned
> 2. aligned to M64BT size
>
> This patch documents this change on the reason and how.
>
> Signed-off-by: Wei Yang
> ---
>
On Wed, Feb 04, 2015 at 03:26:07PM -0600, Bjorn Helgaas wrote:
>On Thu, Jan 15, 2015 at 10:28:02AM +0800, Wei Yang wrote:
>> On PHB3, PF IOV BAR will be covered by M64 BAR to have better PE isolation.
>> Mostly the total_pe number is different from the total_VFs, which will lead
>> to a conflict be
On Wed, Feb 04, 2015 at 03:26:14PM -0600, Bjorn Helgaas wrote:
>On Thu, Jan 15, 2015 at 10:28:03AM +0800, Wei Yang wrote:
>> This patch implements the pcibios_iov_resource_alignment() on powernv
>> platform.
>>
>> On PowerNV platform, there are 3 cases for the IOV BAR:
>> 1. initial state, the IOV
Hello Greg,
Thanks for looking at this
On 02/04/2015 12:40 PM, Greg KH wrote:
> On Wed, Feb 04, 2015 at 08:48:32AM -0600, Emil Medve wrote:
>>
>> Hello,
>>
>>
>> This is the first attempt to publish the Freescale DPAA B/QMan drivers. They
>> are
>> not to be applied yet. At this stage, this is
On Thu, Jan 15, 2015 at 10:28:06AM +0800, Wei Yang wrote:
> M64 aperture size is limited on PHB3. When the IOV BAR is too big, this
> will exceed the limitation and failed to be assigned.
>
> This patch introduce a different mechanism based on the IOV BAR size:
>
> IOV BAR size is smaller than 64
On Thu, Jan 15, 2015 at 10:28:03AM +0800, Wei Yang wrote:
> This patch implements the pcibios_iov_resource_alignment() on powernv
> platform.
>
> On PowerNV platform, there are 3 cases for the IOV BAR:
> 1. initial state, the IOV BAR size is multiple times of VF BAR size
> 2. after expanded, the I
On Thu, Jan 15, 2015 at 10:28:02AM +0800, Wei Yang wrote:
> On PHB3, PF IOV BAR will be covered by M64 BAR to have better PE isolation.
> Mostly the total_pe number is different from the total_VFs, which will lead
> to a conflict between MMIO space and the PE number.
>
> For example, total_VFs is
From: Christophe Leroy
Date: Mon, 2 Feb 2015 18:06:54 +0100 (CET)
> Freescale ethernet controllers have the capability to re-assemble fragmented
> data into a single ethernet frame. This patch uses this capability and
> implements NETIP_F_SG feature into the fs_enet ethernet driver.
>
> On a MP
On Wed, Feb 04, 2015 at 11:34:09AM +0800, Wei Yang wrote:
> On Tue, Feb 03, 2015 at 06:19:26PM -0600, Bjorn Helgaas wrote:
> >On Tue, Feb 03, 2015 at 03:01:43PM +0800, Wei Yang wrote:
> >> The actual IOV BAR range is determined by the start address and the actual
> >> size for vf_num VFs BAR. After
From: Markus Elfring
Date: Wed, 4 Feb 2015 21:32:27 +0100
The of_node_put() function tests whether its argument is NULL and then
returns immediately. Thus the test around the call is not needed.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring
---
driver
On Wed, Feb 04, 2015 at 08:48:32AM -0600, Emil Medve wrote:
>
> Hello,
>
>
> This is the first attempt to publish the Freescale DPAA B/QMan drivers. They
> are
> not to be applied yet. At this stage, this is more or less the drivers from
> the
> Freescale PowerPC SDK roughly squashed and spli
On Thu, Feb 05, 2015 at 12:08:50AM +0800, Wei Yang wrote:
> Bjorn, this is an error introduced in the patch "PCI: Store individual VF BAR
> size in struct pci_sriov".
>
> This patch is based on the pci/virtualization branch. I have tried, it could
> merge with the bad one cleanly.
>
> Signed-off-
Bjorn, this is an error introduced in the patch "PCI: Store individual VF BAR
size in struct pci_sriov".
This patch is based on the pci/virtualization branch. I have tried, it could
merge with the bad one cleanly.
Signed-off-by: Wei Yang
---
drivers/pci/iov.c | 8
1 file changed, 4 ins
On Wed, Feb 04, 2015 at 08:19:14AM -0600, Bjorn Helgaas wrote:
>On Tue, Feb 3, 2015 at 9:34 PM, Wei Yang wrote:
>> On Tue, Feb 03, 2015 at 06:19:26PM -0600, Bjorn Helgaas wrote:
>>>On Tue, Feb 03, 2015 at 03:01:43PM +0800, Wei Yang wrote:
>
+vf_num = pdn->vf_pes;
>>>
>>>I can't actually b
From: Geoff Thorpe
Change-Id: I59de17c040cdd304f86306336fcf89f130f7db2d
Signed-off-by: Geoff Thorpe
---
arch/powerpc/Kconfig | 33 +++
arch/powerpc/platforms/85xx/Kconfig | 11 +
arch/powerpc/platforms/85xx/corenet_generic.c | 2
From: Geoff Thorpe
Change-Id: I59a75a91b289193b5ab1d30a08f60119dc4d7568
Signed-off-by: Geoff Thorpe
---
drivers/staging/fsl_qbman/Kconfig|7 +
drivers/staging/fsl_qbman/Makefile |2 +
drivers/staging/fsl_qbman/qman_debugfs.c | 1326 ++
drivers/s
From: Geoff Thorpe
Change-Id: If1b44bb013addc1e855c73a4e6ff74bc8b6e4829
Signed-off-by: Geoff Thorpe
---
drivers/staging/fsl_qbman/Kconfig| 26
drivers/staging/fsl_qbman/Makefile | 16 ++-
drivers/staging/fsl_qbman/bman_test.c| 56
drivers/staging/f
Hello,
This is the first attempt to publish the Freescale DPAA B/QMan drivers. They are
not to be applied yet. At this stage, this is more or less the drivers from the
Freescale PowerPC SDK roughly squashed and split in a sequence of component
patches. They still needs some work and cleanup bef
From: Geoff Thorpe
Change-Id: I7eea7aea8a58ad0c28451b70801c0d101e88d263
Signed-off-by: Geoff Thorpe
---
drivers/staging/fsl_qbman/Kconfig| 7 ++
drivers/staging/fsl_qbman/Makefile | 2 +
drivers/staging/fsl_qbman/bman_debugfs.c | 119 +++
drivers/st
From: Geoff Thorpe
Change-Id: I59de17c040cdd304f86306336fcf89f130f7db2d
Signed-off-by: Geoff Thorpe
---
arch/powerpc/platforms/85xx/corenet_generic.c | 8 +++-
arch/powerpc/platforms/85xx/p1023_rdb.c | 8 +++-
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/arch/po
From: Hai-Ying Wang
Change-Id: I863d5c15c7f35f9de4ea3d985e4ff467167924b7
Signed-off-by: Hai-Ying Wang
---
drivers/staging/fsl_qbman/bman_driver.c | 45 -
1 file changed, 44 insertions(+), 1 deletion(-)
diff --git a/drivers/staging/fsl_qbman/bman_driver.c
b/driv
From: Geoff Thorpe
Change-Id: I314d36d94717cfc34053b6212899f71cb729d16c
Signed-off-by: Geoff Thorpe
---
drivers/staging/fsl_qbman/Kconfig | 24 ++
drivers/staging/fsl_qbman/Makefile | 24 +-
drivers/staging/fsl_qbman/qman_test.c | 57 +++
drivers/staging/
From: Hai-Ying Wang
Change-Id: Ica4d1b2b0fd3c3ae5e043663febd9f4cb7c762cf
Signed-off-by: Hai-Ying Wang
---
drivers/staging/fsl_qbman/qman_driver.c | 45 +
1 file changed, 45 insertions(+)
diff --git a/drivers/staging/fsl_qbman/qman_driver.c
b/drivers/staging/fsl
CR only needs to be preserved when checking if we are handling a kernel address.
So we can preserve CR in a register:
- In ITLBMiss, check is done only when CONFIG_MODULES is defined. Otherwise we
don't need to do anything at all with CR.
- We use r10, then we reload SRR0/MD_EPN into r10 when CR is
By default, TASK_SIZE is set to 0x8000 for PPC_8xx, which is most likely
sufficient for most cases. However, kernel configuration allows to set TASK_SIZE
to another value, so the 8xx shall handle it.
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change (but impacted by patch 07)
v
In order to be able to reduce scope during which CR is saved, we take
CR saving/restoring out of exception PROLOG and EPILOG
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change (but impacted by patch 07)
v4: Respined against scootwood.git next (0dc294f7)
arch/powerpc/kernel/head_8x
Having a macro will help keep clear code.
Signed-off-by: Christophe Leroy
---
v2: no change
v3: Fixed the macro (missing -) and changed macro name to be more explicit
v4: Respined against scootwood.git next (0dc294f7)
arch/powerpc/kernel/head_8xx.S | 18 --
1 file changed, 12 i
We now have SPRG2 available as in it not used anymore for saving CR, so we don't
need to crash DAR anymore for saving r3 for CPU6 ERRATA handling.
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: Respined against scootwood.git next (0dc294f7)
arch/powerpc/kernel/head_8xx.S |
This patchset provides a further optimisation of TLB handling in the 8xx.
Changes are:
- Not saving registers like CR when not needed
- Adding support to any TASK_SIZE
Patchset:
01 - powerpc/8xx: macro for handling CPU15 errata
02 - powerpc/8xx: Handle CR out of exception PROLOG/EPILOG
03 - powerp
On 03.02.15 06:36, David Gibson wrote:
> Sometimes the KVM code on powerpc needs to emulate load or store
> instructions from the guest, which can include both normal and byte
> reversed forms.
>
> We currently (AFAICT) handle this correctly, but some variable names are
> very misleading. In pa
On Tue, Feb 3, 2015 at 9:34 PM, Wei Yang wrote:
> On Tue, Feb 03, 2015 at 06:19:26PM -0600, Bjorn Helgaas wrote:
>>On Tue, Feb 03, 2015 at 03:01:43PM +0800, Wei Yang wrote:
>>> +vf_num = pdn->vf_pes;
>>
>>I can't actually build this, but I don't think pdn->vf_pes is defined yet.
>>
>
> The pd
On Wed, Feb 04, 2015 at 11:54:39AM +, David Laight wrote:
> From: David Gibson
> > arch/powerpc/include/asm/swab.h includes some powerpc specific
> > byteswapping functions, which are implemented in terms of powerpc's
> > built in byte reversed load/store instructions. There are two problems
On 03.02.15 01:12, Alex Williamson wrote:
> On Thu, 2015-01-29 at 20:21 +1100, Alexey Kardashevskiy wrote:
>> Modern IBM POWERPC systems support multiple (currently two) TCE tables
>> per IOMMU group (a.k.a. PE). This adds a powerpc_iommu container
>> for TCE tables. Right now just one table is s
From: David Gibson
> arch/powerpc/include/asm/swab.h includes some powerpc specific
> byteswapping functions, which are implemented in terms of powerpc's
> built in byte reversed load/store instructions. There are two problems with
> this:
>
> 1) They're not necessary - gcc is perfectly capable
On Sat, Jan 31, 2015 at 2:47 PM, Kevin Hao wrote:
> The PPC_OF is a ppc specific option which is used to mean that the
> firmware device tree access functions are available. Since all the
> ppc platforms have a device tree, it is aways set to 'y' for ppc.
> So it makes no sense to keep a such opt
On 02/04/2015 01:51 PM, Anshuman Khandual wrote:
> On 01/13/2015 03:52 PM, Anshuman Khandual wrote:
>> >This patch series has patches for POWER DSCR fixes, improvements,
>> > in code documentaion, kernel support user documentation and selftest based
>> > test cases. It has got five test cases w
On 01/13/2015 03:52 PM, Anshuman Khandual wrote:
> This patch series has patches for POWER DSCR fixes, improvements,
> in code documentaion, kernel support user documentation and selftest based
> test cases. It has got five test cases which are derived from Anton's DSCR
> test bucket which ca
From: Ian Munsie
We were missing a return statement in the PSL interrupt handler in the
case of an AFU error, which would trigger an "Unhandled CXL PSL IRQ"
warning. We do actually handle these type of errors (by notifying
userspace), so add the missing return IRQ_HANDLED so we don't throw
uneces
From: Ian Munsie
If an AFU claims to have a configuration record but doesn't actually
contain a vendor and device ID, fail the AFU initialisation. Right now
this is just a way of politely letting AFU developers know that they
need to fix their config space, but later on we may expose the AFUs as
From: Ian Munsie
An AFU may optionally contain one or more PCIe like configuration
records, which can be used to identify the AFU.
This patch adds support for exposing the raw config space and the
vendor, device and class code under sysfs. These will appear in a
subdirectory of the AFU device co
52 matches
Mail list logo
